Abstract: A method of programming a memory array including a plurality of memory cells is provided. The memory cells may include phase-change memory elements. In one aspect, the method includes applying in succession first through nth current pulses to each of the memory cells to be programmed to a first state (e.g., a crystalline state), where a current amplitude of the first through nth current pulses decreases with each successive pulse, and where a pulse duration of the first through nth current pulses increases with each successive pulse.

Abstract: Phase-changeable random access memory (PRAM) devices include a plurality of rows and columns of PRAM memory cells therein and at least one local bit line electrically coupled to a column of the PRAM memory cells. First and second bit line selection circuits are provided to increase the rate at which the at least one local bit line can be accessed and driven with a bit line signal. These first and second bit line selection circuits are configured to electrically connect first and second ends of the at least one local bit line to a global bit line during an operation to read data from a selected one of the PRAM memory cells in the column.

Abstract: A semiconductor memory device includes a plurality of wordline driving circuits adapted to control the voltage level of a sub-wordline in response to a logic state of a global wordline and an address signal. The wordline driving circuit comprises first and second transistors configured to maintain the sub-wordline at a first voltage level when the global wordline and the address signal have a first logic state and at a second voltage level when the global wordline or the address signal have a second logic state.

Abstract: A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

Abstract: Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of p

Abstract: A method of biasing a memory cell array during a data writing operation and a semiconductor memory device are provided. The semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.

Abstract: A redundancy circuit in a semiconductor memory device having a multiblock structure in which a memory cell array is classified into a plurality of memory cell blocks, an integrated redundancy circuit having a plurality of fuse boxes for storing, per block, addresses of defective memory cells provided in the plurality of memory cell blocks, the plurality of fuse boxes being connected to the common precharge unit and being selectively activated in response to a block distinction selection signal.

Abstract: A reference voltage generating circuit includes a current mirror circuit having first and second current paths formed between a first power source terminal and a second power source terminal in which the current mirror circuit is operated in response to a voltage level of the second current path, a reference voltage output node for providing a reference voltage and being located on the second current path, an active resistance device formed on the first current path to be operated in a linear region of a current-voltage characteristic curve of the active resistance device, and a voltage supply circuit for supplying the active resistance device with an enable voltage to control the active resistance device to be operated in the linear region.

Abstract: In a semiconductor memory device and method, phase-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices formed of a phase-change material. Each phase-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of phase-change memory cell groups storing data while being connected to the local bit lines, respectively.

Abstract: A flip chip interface circuit for combining two identical semiconductor chips on upper and lower surfaces of an assembling lead frame into one flip chip package includes at least first and second address pads and first and second bonding option pads formed symmetrically on the chips in a mirror type arrangement to each other. The first and second address pads are input with a signal for selecting operations of the first and second semiconductor chips. The first and second input pad selection and chip selection signals are output in response to signals from the first and second address pads and first and second bonding option pads of the chips, the first and second semiconductor chip selection signals are output in response to the first and second input pad and chip selection signals, and an interface enable signal is output in response to the first and second semiconductor chip selection signals.

Abstract: Phase-change memory devices are provided that include a plurality of phase-change memory cells and a reset pulse generation circuit configured to output a plurality of sequential reset pulses. Each sequential reset pulse is output to a corresponding one of a plurality of reset lines. A plurality of write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit. Methods of programming phase-change memory devices using sequential reset control signals are also provided.

Abstract: A memory device includes a plurality of blocks, with each block having a respective array of memory cells and respective local word lines. The memory device also includes a respective switching device coupled between each local word line and a common voltage node. A global word line driver controls the respective switching devices to turn on for respective local word lines in a row across the blocks including an accessed memory cell. Thus, the common voltage node is in the current path of the accessed memory cell with minimized layout area and resistance of the current path.

Abstract: A phase random access memory including a plurality of access transistors, each access transistor including a drain region, and a phase-changeable film shared by the plurality of access transistors. The phase-changeable film is connected to a bitline through a first electrode and connected to each respective drain region through at least one of a plurality of second electrodes.

Abstract: A phase random access memory including a plurality of access transistors, each access transistor including a drain region, and a phase-changeable film shared by the plurality of access transistors. The phase-changeable film is connected to a bitline through a first electrode and connected to each respective drain region through at least one of a plurality of second electrodes.

Abstract: A method for programming a phase-change memory array and circuit of a phase-change memory device, each having a plurality of phase-change memory cells, may enable all the phase-change memory cells therein to be changed or set at a set resistance state, and may reduce the time needed to change the phase-change memory array to the set resistance state. In the method, a set current pulse having first through nth stages may be applied to the cells of the array to change the cells to the set resistance state. A minimum current level of the set current pulse applied to the phase-change memory cells in any stage may be higher than a reference current level for the cells of the array. A given current level of the set current pulse may be sequentially reduced from stage to stage.

Abstract: A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

Abstract: A firing method of a phase change memory device and a phase change memory capable of effectively performing a firing operation are described. The phase change memory device includes a plurality of memory cell array blocks, a counter clock generation unit, a decoding unit, and a driving unit. Each memory cell array block has phase change memory cells. The counter clock generation unit outputs first through third counter clock signals in response to an external clock signal and a firing mode signal, wherein the first through third counter clock signals have different cycles. The decoding unit, in response to the first through third counter clock signals, outputs a block address which selects one of the plurality of memory cell array blocks, word line addresses which enable word lines of the selected memory cell array block, and a redundant word line address which enables a redundant word line of the selected memory cell array block.

Abstract: A redundancy circuit in a semiconductor memory device having a multiblock structure in which a memory cell array is classified into a plurality of memory cell blocks, an integrated redundancy circuit having a plurality of fuse boxes for storing, per block, addresses of defective memory cells provided in the plurality of memory cell blocks, the plurality of fuse boxes being connected to the common precharge unit and being selectively activated in response to a block distinction selection signal.

Abstract: A phase random access memory including a plurality of access transistors, each access transistor including a drain region, and a phase-changeable film shared by the plurality of access transistors. The phase-changeable film is connected to a bitline through a first electrode and connected to each respective drain region through at least one of a plurality of second electrodes.

Abstract: An integrated circuit that is capable of being burn-in tested with an AC stress and a testing method using the same are provided. The integrated circuit includes an address transforming means and a data generating means. The address transforming means transforms the addresses of the memory device selected and generates an address signal responsive to a clock signal. The data generating means generates a data signal that alternates between a first state and a second state responsive to the clock signal and provides the data signal to the selected memory device. The integrated circuit includes a switch for coupling the test supply line to the normal supply line during testing and intercepting the test supply line from the normal supply line during normal operations responsive to a control signal. The integrated circuit of the present invention allows a wafer burn-in test by sequentially and repeatedly applying the AC stress to all the memory devices.