Abstract: A semiconductor memory device and fabrication method of same includes the processes of forming sacrifice gates on a silicon substrate with the sacrifice gates apart from each other. A first conductive layer is formed on an exposed portion of the silicon substrate between the sacrifice gates and a first inter-insulation layer is formed that exposes the first conductive layer and the sacrifice gates. The exposed sacrifice gates are removed to form openings and damascene gates are subsequently formed in the openings. Capping layers are formed on the top of the gates and a second conductive layer is formed on the exposed first conductive layer. A second inter-insulation layer is formed on the silicon substrate, and bit line contacts that expose the second conductive layer are formed by etching the second inter-insulation layer.

Abstract: a A MOS (metal oxide semiconductor) transistor with a trench-type gate is fabricated with a channel stopping region for forming an asymmetric channel region for reducing short channel effects. For example in fabricating an N-channel MOS transistor, a gate structure is formed within a trench that is within a P-well. A channel stopping region with a P-type dopant is formed to a first side of the trench to completely contain an N-type source junction therein. An N-type drain junction is formed within a LDD region to a second side of the trench, thus forming the asymmetric channel region.

Abstract: A semiconductor memory device includes a silicon substrate with a gate and contact pads at both sides of the gate, an inter-insulation layer formed on the substrate, including a storage node contact and a bit-line contact exposing a corresponding contact pad, and including a groove-shaped bit-line pattern, a storage node contact plug formed in the storage node contact, and a damascene bit line formed within the bit-line pattern and connected with the exposed corresponding contact pad through the bit-line contact.

Abstract: A semiconductor memory device and fabrication method of same includes the processes of forming sacrifice gates on a silicon substrate with the sacrifice gates apart from each other. A first conductive layer is formed on an exposed portion of the silicon substrate between the sacrifice gates and a first inter-insulation layer is formed that exposes the first conductive layer and the sacrifice gates. The exposed sacrifice gates are removed to form openings and damascene gates are subsequently formed in the openings. Capping layers are formed on the top of the gates and a second conductive layer is formed on the exposed first conductive layer. A second inter-insulation layer is formed on the silicon substrate, and bit line contacts that expose the second conductive layer are formed by etching the second inter-insulation layer.

Abstract: A semiconductor memory device includes a silicon substrate with a gate and contact pads at both sides of the gate, an inter-insulation layer formed on the substrate, including a storage node contact and a bit-line contact exposing a corresponding contact pad, and including a groove-shaped bit-line pattern, a storage node contact plug formed in the storage node contact, and a damascene bit line formed within the bit-line pattern and connected with the exposed corresponding contact pad through the bit-line contact.

Abstract: A semiconductor memory device and fabrication method of same includes the processes of forming sacrifice gates on a silicon substrate with the sacrifice gates apart from each other. A first conductive layer is formed on an exposed portion of the silicon substrate between the sacrifice gates and a first inter-insulation layer is formed that exposes the first conductive layer and the sacrifice gates. The exposed sacrifice gates are removed to form openings and damascene gates are subsequently formed in the openings. Capping layers are formed on the top of the gates and a second conductive layer is formed on the exposed first conductive layer. A second inter-insulation layer is formed on the silicon substrate, and bit line contacts that expose the second conductive layer are formed by etching the second inter-insulation layer.

Abstract: Method for forming an oxide film in a semiconductor device, is disclosed, which is suitable to form oxide films of different thicknesses in a device region, to which driving voltages of different levels are applied respectively, including the steps of providing a semiconductor substrate, forming an insulating film on the semiconductor substrate, injecting first, and second impurity ions into the semiconductor substrate through the exposed insulating film after masking required regions of the insulating film, removing the insulating film, and forming first, and second oxide films having thicknesses different from each other on regions of the semiconductor substrate having the impurity ions are injected and the impurity ions are not injected thereto, respectively.

Abstract: A fabrication method for a semiconductor memory device includes the steps of forming a gate pattern on a semiconductor substrate; forming first and second sidewall spacers at sides of the gate pattern; performing an ion=implantation of a high concentration impurity using the gate pattern and the first and second sidewall spacers as a mask, thereby forming an impurity diffusion region in the semiconductor substrate; performing an ion-implantation of a transition metal on the semiconductor substrate including the gate pattern and the first and second sidewall spacers, and then forming a polysilicide and a silicide by annealing; and removing the second sidewall spacers.

Abstract: A method of fabricating a semiconductor device includes the steps of sequentially forming a gate oxide layer, a gate material layer and a cap insulating layer on a semiconductor substrate, selectively etching them to form a gate, sequentially forming a plurality of material layers on the overall surface of the semiconductor substrate including the gate, etching them back to form a gate sidewall spacer out of the plurality of material layers, and selectively removing the plurality of material layers forming the gate sidewall spacer to form gate sidewall spacers having lengths different from each other, the lengths depending on a particular region of the substrate.

Abstract: A semiconductor fabrication method for forming an insulation film and a first anti-oxidation film sequentially on a substrate which is sectioned into each of a peri region and a cell region. An active pattern is formed in the cell region and a first field ion-implanted region in a first conductive well of the cell region. Side wall spacers are formed on each side wall of the active pattern in the cell region. An active pattern is formed in the peri region by selectively etching the first anti-oxidation film and the insulation film so as to expose a certain surface portion of the peri region substrate therethrough. A first field ion-implanting region is formed in a first conductive well of the peri region by ion-implanting highly concentrated first conductive impurities through the exposed substrate and a second field ion-implanted region in a second conductive well of the peri region.

Abstract: A method for forming an isolation region of a semiconductor device to improve isolation characteristics between semiconductor devices. A first insulating layer is formed on a substrate, and a second insulating layer is formed on the first insulating layer. A field region of the substrate is defined by selectively removing the second insulating layer. A portion of the surface of the substrate is then exposed by selectively removing the first insulating layer using the second insulating layer as a mask. A third insulating layer is formed on the exposed portion of the substrate. Then insulating sidewalls are formed on sides of the first and second insulating layers. Next, a trench is then formed in the substrate using the second insulating layer and the insulating sidewalls as masks. Finally, a field oxide layer is formed in the trench to isolate semiconductor devices.

Abstract: A fabrication method for a semiconductor device which is capable of preventing the shorting of the semiconductor device by performing an ion-implantation of an impurity after forming an insulating layer on a gate electrode, and forming sidewall spacers on the upper surface of the gate electrode and at the sides thereof includes: forming on a semiconductor substrate a pattern including a gate insulating film, a gate electrode on the gate insulating film and a disposable layer on the gate electrode; forming low concentration impurity regions in the substrate by performing an ion implantation, using the pattern as a mask; forming first sidewall spacers at the sides of the pattern; forming high concentration impurity regions in the substrate by performing an ion implantation, using the pattern and the sidewall spacers as a mask; stripping the disposable layer; forming second sidewall spacers at the sides of the first sidewall spacers and on both ends of the upper surface of the gate electrode; and forming a react