Abstract: A semiconductor memory device includes a core region for storing data and a peripheral region for controlling the core region. The semiconductor memory device includes a digital noise measurement circuit and an output selection circuit. The digital noise measurement circuit selects a first operation voltage among a plurality of operation voltages based on a voltage selection signal, generates first noise data by digitizing first noise in the first operation voltage based on a plurality of reference voltages, and outputs the first noise data. The plurality of operation voltages are supplied to the core region and the peripheral region. The output selection circuit outputs one of first data and the first noise data based on an output selection signal. The first data is provided from the core region.

Abstract: A semiconductor memory device includes a core region for storing data and a peripheral region for controlling the core region. The semiconductor memory device includes a digital noise measurement circuit and an output selection circuit. The digital noise measurement circuit selects a first operation voltage among a plurality of operation voltages based on a voltage selection signal, generates first noise data by digitizing first noise in the first operation voltage based on a plurality of reference voltages, and outputs the first noise data. The plurality of operation voltages are supplied to the core region and the peripheral region. The output selection circuit outputs one of first data and the first noise data based on an output selection signal. The first data is provided from the core region.

Abstract: A semiconductor memory device includes a first row of pads including a first plurality of data input/output (I/O) pads; a second row of pads including a second plurality of data I/O pads; and a first I/O multiplexer associated with the first row of pads and providing first output data only to at least one data I/O pad of the first row of pads, even after a data I/O mode of the semiconductor memory device has changed. The semiconductor memory device also includes a second I/O multiplexer associated with the second row of pads and providing second output data only to at least one data I/O pad of the second row of pads, even after the data I/O mode has changed.

Abstract: A semiconductor memory device includes a memory cell array a redundant enable signal generating circuit and redundant decoder. The memory cell array includes memory cell array blocks including column selecting signal lines and lower and upper blocks. The redundant enable signal generating circuit programming defective addresses, during a mode setting operation and generating a redundant enable signal when the defective addresses are applied during an operation. The redundant decoder including decoders selecting a corresponding redundant column selecting signal line in response to the redundant enable signal, a corresponding block address, and a lower and upper block address, wherein each of the of decoders is electrically connected to one of the lower and upper blocks.

Abstract: In an embodiment, a semiconductor memory device has a small number of repair signal transmission lines. The semiconductor memory device includes m repair redundancy blocks, each including n repair redundant word lines, and m and n being natural numbers; and a control circuit generating n repair information signals to select the n repair redundant word lines and m block selection information signals to select the m repair redundancy blocks, and transmitting the n repair information signals and the m block selection information signals to the m repair redundancy blocks. The n repair information signals are shared by the m repair redundancy blocks. The control circuit includes n×m unit fuse boxes, n unit fuse boxes of which corresponding to each of the m repair redundancy blocks.

Abstract: Embodiments of the invention provide a semiconductor memory device. In one embodiment, the invention provides a semiconductor memory device comprising a first row of pads comprising a first plurality of data input/output pads; a second row of pads comprising a second plurality of data input/output pads; and a first input/output multiplexer associated with the first row of pads and adapted to provide first output data only to at least one data input/output pad of the first row of pads, even after a data input/output mode of the semiconductor memory device has changed. The semiconductor memory device further comprises a second input/output multiplexer associated with the second row of pads and adapted to provide second output data only to at least one data input/output pad of the second row of pads, even after the data input/output mode has changed.

Abstract: A method of configuring a memory cell array block includes dividing a first unit logic block into sub-array blocks and assigning a portion of the sub-array blocks to a second unit logic block, wherein the memory cell array block corresponds to the portion of the sub-array blocks and the second unit logic block, and the portion of the sub-array blocks and the second unit logic block share a peripheral circuit. The first unit logic block may be divided into the sub-array blocks based on a unit of a word line and/or a unit of a bit line. The peripheral circuit may include a row decoder, a column decoder, a sense amplifier and/or an equalize/precharge circuit. A related addressing method, a memory cell array block and semiconductor memory device are also provided.

Abstract: A semiconductor memory device includes a memory cell array a redundant enable signal generating circuit and redundant decoder. The memory cell array includes memory cell array blocks including column selecting signal lines and lower and upper blocks. The redundant enable signal generating circuit programming defective addresses, during a mode setting operation and generating a redundant enable signal when the defective addresses are applied during an operation. The redundant decoder including decoders selecting a corresponding redundant column selecting signal line in response to the redundant enable signal, a corresponding block address, and a lower and upper block address, wherein each of the of decoders is electrically connected to one of the lower and upper blocks.

Abstract: A signal amplification circuit for a semiconductor memory device includes a current sense amplifier configured to receive a first signal pair and generate a second signal pair on a first pair of lines, an equalizer configured to equalize the first pair of lines, and a latch amplifier configured to generate a latch data output on a second pair of lines in response to the second signal pair.

Abstract: A circuit for controlling timing skew in a semiconductor memory device includes a skew control circuit that is configured generate separate skew control signals for each respective one of a plurality of memory banks included in the semiconductor memory device. Related methods are also disclosed.

Abstract: A method of configuring a memory cell array block includes dividing a first unit logic block into sub-array blocks and assigning a portion of the sub-array blocks to a second unit logic block, wherein the memory cell array block corresponds to the portion of the sub-array blocks and the second unit logic block, and the portion of the sub-array blocks and the second unit logic block share a peripheral circuit. The first unit logic block may be divided into the sub-array blocks based on a unit of a word line and/or a unit of a bit line. The peripheral circuit may include a row decoder, a column decoder, a sense amplifier and/or an equalize/precharge circuit. A related addressing method, a memory cell array block and semiconductor memory device are also provided.

Abstract: In an embodiment, a semiconductor memory device has a small number of repair signal transmission lines. The semiconductor memory device includes m repair redundancy blocks, each including n repair redundant word lines, and m and n being natural numbers; and a control circuit generating n repair information signals to select the n repair redundant word lines and m block selection information signals to select the m repair redundancy blocks, and transmitting the n repair information signals and the m block selection information signals to the m repair redundancy blocks. The n repair information signals are shared by the m repair redundancy blocks. The control circuit includes n×m unit fuse boxes, n unit fuse boxes of which corresponding to each of the m repair redundancy blocks.

Abstract: A pipeline memory device including a data fetching control circuit and utilizes a data fetching method. The pipeline memory device includes a first, second, and third pipeline stages. A second pipeline control signal, for operating the second pipeline stage, is generated from a first pipeline control signal. The data fetching control circuit includes the following: A first edge trigger delay circuit that receives the clock signal for generating the first pipeline control signal and generates the first pipeline control signal. A second edge trigger delay circuit that receives the clock signal for generating the first pipeline control signal. A first inverter that inverts the first pipeline control signal. A NAND gate that inputs the outputs of the first inverter and the second edge trigger delay circuit. A second inverter that inverts the output of the NAND gate to output the second pipeline control signal.