Patents by Inventor Duane Arlyn Averill

Duane Arlyn Averill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7788452
    Abstract: A computer system includes multiple caches and a cache line state directory structure, having at least a portion dedicated to a particular device cache within a particular device, and contains a fixed number of entries having a one-to-one correspondence to the cache lines of the cache to which it corresponds. The cache line state directory is used to determine whether it is necessary to send an invalidation message to the device cache. In the preferred embodiment, a dedicated portion of the cache line state directory structure corresponds to an I/O bridge device cache. Preferably, the cache line state directory also maintains state for one or more processor caches in a different format. The computer system preferably uses a NUMA architecture, the directories being maintained by node servers in each node.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: August 31, 2010
    Assignee: International Business Machines Corporation
    Inventors: Duane Arlyn Averill, Russell Dean Hoover, David Alan Shedivy, Martha Ellen Voytovich
  • Patent number: 7467260
    Abstract: An apparatus and method is disclosed for flushing a cache in a computing system. In a multinode computing system a cache in a first node may contain modified data in an address space of a second node. The cache in the first node must be purged prior to shutting down the first node. The computing system uses a random class replacement scheme for the cache. A cache flush routine sets a cache flush mode in a class replace select mechanism, overriding the random class replacement scheme. With the random class replacement scheme overridden, a minimum number of fetches will flush all the cache lines in the cache, each fetch loading the cache with a cache line not already in the cache. No additional delay penalty is incurred in a critical path through which fetches and stores to the cache must pass.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: December 16, 2008
    Assignee: International Business Machines Corporation
    Inventors: Duane Arlyn Averill, John Michael Borkenhagen, Philip Rogers Hillier, III
  • Publication number: 20080307169
    Abstract: A data processing system includes a coherence directory having a prefetch sector cache and a memory directory array containing a plurality of sectored entries. According to one method, in response to receiving a first directory lookup request specifying a first target address, an entry associated with the target address is accessed in the memory directory array. In response to the access, the coherence directory returns, as a result of the first directory lookup request, contents of a first sector that is identified by the target address as a requested sector. The coherence directory also caches contents of a second sector of the multiple sectors that is a non-requested sector for the first directory lookup request in a prefetch sector cache.
    Type: Application
    Filed: June 6, 2007
    Publication date: December 11, 2008
    Inventors: Duane Arlyn Averill, Jonathon C. Skarphol, Brian T. Vanderpool
  • Patent number: 6263404
    Abstract: A memory cache sequencer circuit manages the operation of a memory cache and cache buffer so as to efficiently forward memory contents being delivered to the memory cache via the cache buffer, to a multithreading processor awaiting return of those memory contents. The sequencer circuit predicts the location of the memory contents that the processor is awaiting, and speculatively forwards memory contents from either the cache buffer or memory cache, while simultaneously verifying that the speculatively forwarded memory contents were correctly forwarded. If the memory contents were incorrectly forwarded, the sequencer circuit issues a signal to the processor receiving the speculatively forwarded memory contents to ignore the forwarded memory contents. This speculative forwarding process may be performed, for example, when a memory access request is received from the processor, or whenever memory contents are delivered to the cache buffer after a cache miss.
    Type: Grant
    Filed: November 21, 1997
    Date of Patent: July 17, 2001
    Assignee: International Business Machines Corporation
    Inventors: John Michael Borkenhagen, Duane Arlyn Averill
  • Patent number: 6044447
    Abstract: A method and apparatus are provided for communicating translation command information in a multithreaded environment in a computer system. The computer system includes a processor unit, an instruction unit coupled to the processor unit, a cache coupled to the processor unit, a main memory, and a storage control unit including a dataflow control partition, a cache control partition, a translation control partition. A translation miss signal is sent from the dataflow control partition to the translation control partition, responsive to detecting a translation miss condition. A translation command next signal is sent from the translation control partition to the cache control partition responsive to the translation miss signal. Then a translation command signal is sent from the translation control partition to the cache control partition.
    Type: Grant
    Filed: January 30, 1998
    Date of Patent: March 28, 2000
    Assignee: International Business Machines Corporation
    Inventors: Duane Arlyn Averill, John Michael Borkenhagen, James Anthony Steenburgh, Sandra S. Woodward