Abstract: In one embodiment, a method for forming a semiconductor device includes forming trench and a dielectric layer along surfaces of the trench. A shield electrode is formed in a lower portion of the trench and the dielectric layer is removed from upper sidewall surfaces of the trench. A gate dielectric layer is formed along the upper surfaces of the trench. Oxidation-resistant spacers are formed along the gate dielectric layer. Thereafter, an interpoly dielectric layer is formed above the shield electrode using localized oxidation. The oxidation step increases the thickness of lower portions of the gate dielectric layer. The oxidation-resistant spacers are removed before forming a gate electrode adjacent the gate dielectric layer.

Abstract: A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.

Abstract: A method of printing an image on a wafer. The method includes the steps of printing a main image, wherein the main image includes fields which are fully on the wafer, and printing an alternate image, wherein the alternate image includes fields which are only partially on the wafer. The alternate image could be placed on a separate mask which is loaded onto the exposure tool after the mask with the main image has completed printing. Alternatively, it could be an extra image specially inserted on the mask with the main image for that layer.

Abstract: In one embodiment, a method for forming a semiconductor device includes forming trench and a dielectric layer along surfaces of the trench. A shield electrode is formed in a lower portion of the trench and the dielectric layer is removed from upper sidewall surfaces of the trench. A gate dielectric layer is formed along the upper surfaces of the trench. Oxidation-resistant spacers are formed along the gate dielectric layer. Thereafter, an interpoly dielectric layer is formed above the shield electrode using localized oxidation. The oxidation step increases the thickness of lower portions of the gate dielectric layer. The oxidation-resistant spacers are removed before forming a gate electrode adjacent the gate dielectric layer.

Abstract: A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.

Abstract: A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.

Abstract: A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.

Abstract: A semiconductor component that includes gate electrodes and shield electrodes and a method of manufacturing the semiconductor component. A semiconductor material has a device region, a gate contact region, a termination region, and a drain contact region. One or more device trenches is formed in the device region and one or more termination trenches is formed in the edge termination region. Shielding electrodes are formed in portions of the device trenches that are adjacent their floors. A gate dielectric material is formed on the sidewalls of the trenches in the device region and gate electrodes are formed over and electrically isolated from the shielding electrodes. The gate electrodes in the trenches in the device region are connected to the gate electrodes in the trenches in the gate contact region. The shielding electrodes in the trenches in the device region are connected to the shielding electrodes in the termination region.

Abstract: A method of fabricating integrated circuits according to a first design. One first pattern is common with a second design, and one second pattern is unique to the first design. The first pattern is imaged using a first mask having first patterns formed in a block thereon. No other patterns of the first and second designs are formed on the first mask. The second patterns are imaged on the substrate using a second mask having second patterns formed in a block thereon. At least one third layer pattern is formed on the second mask.

Abstract: A mask for exposing a first layer and a second layer on a process substrate, where the first and second layers are two separate layers of an integrated circuit. The mask includes a mask substrate that is substantially completely transmissive to a first wavelength of light and a second wavelength of light. A layer of a first material is disposed on the mask substrate, where the first material is substantially opaque to the first wavelength of light. The layer of the first material is patterned for the first layer. A layer of a second material is disposed on the mask substrate, where the second material is substantially opaque to the second wavelength of light. The layer of the second material is patterned for the second layer, where the layer of the first material and the layer of the second material are aligned on the mask substrate for proper alignment of the first and second layers on the process substrate.

Abstract: A method of fabricating integrated circuits according to a first design. One first pattern is common with a second design, and one second pattern is unique to the first design. The first pattern is imaged using a first mask having first patterns formed in a block thereon. No other patterns of the first and second designs are formed on the first mask. The second patterns are imaged on the substrate using a second mask having second patterns formed in a block thereon. At least one third layer pattern is formed on the second mask.

Abstract: A method of fabricating integrated circuits according to a first design by imaging a first layer on a substrate using a first mask having a block of first patterns in common with a second design, but without any other patterns of the first or second designs and imaging a second layer on the substrate using a second mask having a block of second patterns unique to the first design and at least one third layer pattern. The block of first patterns is repeatedly exposed in a first grid and the block of second patterns is repeatedly exposed in a second grid, each without overlap in the corresponding layer. The grids are aligned such that the integrated circuits and test structures in scribe lines between the integrated circuits are properly formed on the substrate. The first patterns can be for large fields and the second patterns can be for small fields.

Abstract: The invention provides a method of measuring a standard critical dimension feature and insuring that this feature is representative of cross-chip average critical dimension size in accordance with an embodiment of the invention. The method includes the steps of incorporating a cluster of CD features, determining a cross-chip average feature size, selecting the CD feature which is closest in size to the cross-chip average CD feature size as the standard feature for in-line measurement, and implementing the CD measurement of the appropriate feature on production wafers.

Abstract: A mask used for imaging nearly dense features in a substrate. Scatter dots are disposed on the mask in proximity to the nearly dense features, where the scatter dots adjust photon levels of the nearly dense features to a desired level. The adjustment is controlled by selective adjustment of a duty cycle and degree of stagger of the scatter dots. In this manner, the scatter dots adjust the optical properties of the nearly dense features to be very similar to the optical properties of dense features, which enables more accurate imaging of the nearly dense features on the substrate. However, because the scatter dots are discontinuous, they do not overcorrect in the same manner that a scatter bar formed at a minimum resolution might overcorrect. Further, there is a reduced likelihood that the scatter dots would actually print on the substrate.

Abstract: A method for leveling an exposure field of view at a peripheral edge of a substrate. The field of view is aligned to a first position at the peripheral edge of the substrate, where the field of view has an inner edge and an outer edge, relative to the peripheral edge of the substrate. Whole device patterns within the field of view are identified, and the alignment of the field of view is altered to a second position so as to place the outer edge of the field of view adjacent the whole device patterns within the field of view. Level measurement information from the field of view at the second position is acquired and stored. The field of view is realigned to the first position, and the substrate is leveled within the field of view at the first position using the level measurement information acquired from the field of view at the second position.

Abstract: A method of fabricating a plurality of integrated circuits on a substrate according to a first integrated circuit design. Each of the integrated circuits is formed with a plurality of layer patterns. At least one first layer pattern of the layer patterns is common with a second integrated circuit design, and at least one second layer pattern of the layer patterns is unique to the first integrated circuit design. The first layer pattern is imaged on the substrate using an exposure tool and a first mask having a first number of the first layer patterns formed in a block thereon. No other layer patterns of the first layer patterns and the second layer patterns are formed on the first mask. The first number is less than the plurality of integrated circuits formed on the substrate. The first layer patterns are imaged on the substrate by exposing and repeating the block of first number of first layer patterns across the substrate with the exposure tool.

Abstract: The invention provides a method of measuring a standard critical dimension feature and insuring that this feature is representative of cross-chip average critical dimension size in accordance with an embodiment of the invention. The method includes the steps of incorporating a cluster of CD features, determining a cross-chip average feature size, selecting the CD feature which is closest in size to the cross-chip average CD feature size as the standard feature for in-line measurement, and implementing the CD measurement of the appropriate feature on production wafers.

Abstract: A method for leveling an exposure field of view at a peripheral edge of a substrate. The field of view is aligned to a first position at the peripheral edge of the substrate, where the field of view has an inner edge and an outer edge, relative to the peripheral edge of the substrate. Whole device patterns within the field of view are identified, and the alignment of the field of view is altered to a second position so as to place the outer edge of the field of view adjacent the whole device patterns within the field of view. Level measurement information from the field of view at the second position is acquired and stored. The field of view is realigned to the first position, and the substrate is leveled within the field of view at the first position using the level measurement information acquired from the field of view at the second position.

Abstract: A mask used for imaging nearly dense features in a substrate. Scatter dots are disposed on the mask in proximity to the nearly dense features, where the scatter dots adjust photon levels of the nearly dense features to a desired level. The adjustment is controlled by selective adjustment of a duty cycle and degree of stagger of the scatter dots. In this manner, the scatter dots adjust the optical properties of the nearly dense features to be very similar to the optical properties of dense features, which enables more accurate imaging of the nearly dense features on the substrate. However, because the scatter dots are discontinuous, they do not overcorrect in the same manner that a scatter bar formed at a minimum resolution might overcorrect. Further, there is a reduced likelihood that the scatter dots would actually print on the substrate.

Abstract: A system of supporting useful payloads via magnetic forces using magnets of unmodulated strength operating in attractive mode without the necessity of complex sensing and control for maintaining a payload lift. Disclosed are embodiments of or lifting, conveying, and/or transporting of loads including various features for enhancing performance and stability thereof.