Abstract: The effects of processing parameters and suspension chemorheology on the deposition behavior of SFF components derived from polymeric-based gelcasting suspensions combines the advantages associated with SFF fabrication, including the ability to spatially tailor composition and structure as well as reduced tooling costs, with the improved handling strength afforded by the use of gel based formulations. As-cast free-formed Al2O3 components exhibited uniform particle packing and had minimal macro-defects (e.g., slumping or stair casing) and no discernable micro-defects (e.g., bubbles or cracking).

Abstract: Applique circuits suitable for advanced packaging applications are introduced. These structures are particularly suited for the simple integration of large amounts (many nanoFarads) of capacitance into conventional integrated circuit and multichip packaging technology. In operation, applique circuits are bonded to the integrated circuit or other appropriate structure at the point where the capacitance is required, thereby minimizing the effects of parasitic coupling. An immediate application is to problems of noise reduction and control in modern high-frequency circuitry.

Abstract: A method is described for altering the luminescence of a light emitting semiconductor (LES) device. In particular, a method is described whereby a silicon LES device can be selectively irradiated with a radiation source effective for altering the intensity of luminescence of the irradiated region.

Abstract: An improved ferroelectric capacitor exhibiting reduced imprint effects in comparison to prior art capacitors. A capacitor according to the present invention includes top and bottom electrodes and a ferroelectric layer sandwiched between the top and bottom electrodes, the ferroelectric layer comprising a perovskite structure of the chemical composition ABO.sub.3 wherein the B-site comprises first and second elements and a dopant element that has an oxidation state greater than +4. The concentration of the dopant is sufficient to reduce shifts in the coercive voltage of the capacitor with time. In the preferred embodiment of the present invention, the ferroelectric element comprises Pb in the A-site, and the first and second elements are Zr and Ti, respectively. The preferred dopant is chosen from the group consisting of Niobium, Tantalum, and Tungsten. In the preferred embodiment of the present invention, the dopant occupies between 1 and 8% of the B-sites.

Abstract: A method is disclosed for fabricating grain boundary junction devices, which comprises preparing a crystalline substrate containing at least one grain boundary therein, epitaxially depositing a high Tc superconducting layer on the substrate, patterning the superconducting layer to leave at least two superconducting regions on either side of the grain boundary and making electrical contacts to the superconducting regions so that bias currents can be produced across the grain boundary.

Abstract: High T.sub.c superconducting devices are described in which controlled grain boundaries in a layer of the superconductors forms a weak link or barrier between superconducting grains of the layer. A method is described for reproducibly fabricating these devices, including first preparing a substrate to include at least one grain boundary therein. A high T.sub.c superconductor layer is then epitaxially deposited on the substrate in order to produce a corresponding grain boundary in the superconducting layer. This superconducting layer is then patterned to leave at least two regions on either side of the grain boundary, the two regions functioning as contact areas for a barrier device including the grain boundary as a current flow barrier. Electrical contacts can be made to the superconducting regions so that bias currents can be produced across the grain boundary which acts as a tunnel barrier or weak link connection.