Abstract: A uniform coating is provided using surface features. Multiple ridges or other shapes are fabricated near an area of interest to allow for uniform coating in between the ridges. Areas at either ends of the ridges are left open to allow for excess pooling of photoresist liquid and to aid in obtaining uniform coating. The photoresist liquid or other coating fluid is applied to the sample and spun dry. A soft-bake process is performed to evaporate remaining solvents. An element, such as a diffractive, refractive, or reflective grating structure, is then formed in the area of interest using the uniform photoresist coating.

Abstract: A uniform coating is provided using surface features. Multiple ridges or other shapes are fabricated near an area of interest to allow for uniform coating in between the ridges. Areas at either ends of the ridges are left open to allow for excess pooling of photoresist liquid and to aid in obtaining uniform coating. The photoresist liquid or other coating fluid is applied to the sample and spun dry. A soft-bake process is performed to evaporate remaining solvents. An element, such as a diffractive, refractive, or reflective grating structure, is then formed in the area of interest using the uniform photoresist coating.

Abstract: A method of isolating an exposed conductive surface. An aluminum layer (130) is selectively formed over the exposed conductive (106) surface (e.g., Cu) but not over the surrounding dielectric (110) surface using a thermal CVD process. The aluminum layer (130) is then oxidized to form a thin isolating aluminum-oxide (108) over only the conductive surface. The isolating aluminum-oxide provides a barrier for the Cu while taking up minimal space and reducing the effective dielectric constant.

Abstract: Contacts for an electronic device are formed by providing a substrate (12) that has at least two access line structures (16) for a memory array (14) and a periphery structure (20) for a peripheral circuit (18) to the memory array (14). A first insulative layer (40) is formed outwardly of the substrate (12), the access line structures (16), and the periphery structure (20). A contact area of the periphery structure (20) is exposed through the first insulative layer (40) while maintaining the first insulative layer (40) over at least a contact overlap portion (48) of the access line structures (16). A second insulative layer (60) is formed outwardly of the substrate (12), the access line structures (16), the periphery structure (20), and the first insulative layer (40).

Abstract: A method of isolating an exposed conductive surface. An aluminum layer (130) is selectively formed over the exposed conductive (106) surface (e.g., Cu) but not over the surrounding dielectric (110) surface using a thermal CVD process. The aluminum layer (130) is then oxidized to form a thin isolating aluminum-oxide (108) over only the conductive surface. The isolating aluminum-oxide provides a barrier for the Cu while taking up minimal space and reducing the effective dielectric constant.

Abstract: A spatial light modulator with an anti-reflective coating (ARC) 100 integrated into its structure. The manufacturing of the device is altered to include deposition of an ARC 100, and any necessary patterning and etching to allow the elements of the array to operate properly. The ARC could reside in several places of the element structure including over the addressing circuitry 26, over a middle layer 32 or on the underside of the reflective structure 10. Micromechanical spatial light modulators, as well as non-moving modulators, such as reflective and transmissive LCD modulators can use the invention.

Abstract: A dry etch using CFx in an O2-rich environment will clean the contact/via at the same time it retracts a layer of TiN enclosed in the dielectric layer, such as the plate layer in a Capacitor-Under-Bitline DRAM cell.

Abstract: A method for fabricating a low resistivity polymetal silicide conductor/gate comprising, the steps of forming a polysilicon (66) over a gate oxide (64) followed by protection of the polysilicon (66) with a sacrificial material (68), is disclosed. Gate sidewalls (70) are created to protect the sides of the polysilicon (66) and the sacrificial material (68), followed by stripped the sacrificial material (68) to expose the top surface of the polysilicon (66). Next, a diffusion barrier (76) is deposited over the exposed polysilicon (66) and a metal layer (78) is selectively grown on the diffusion barrier (76) to form a gate contact and conductor. Finally, a dielectric layer (80) is deposited over the selectively grown metal layer (78), the sidewalls (70) and the gate oxide (64).

Abstract: A metal-poly stack gate structure and associated method for forming a conductive barrier layer between W and poly in the metal-gate stack gate structure. The process includes the steps of depositing doped silicon on a substrate; forming nitride on the deposited silicon; depositing a metal on the nitride to form a metal/nitride/deposited silicon stack; and thermally treating the stack to transform the nitride into a conductive barrier layer between the metal and the deposited silicon. The thermal treatment transforms the nitride layer (SiN.sub.x or SiN.sub.x O.sub.y) into a conductive barrier (WSi.sub.x N.sub.y or WSi.sub.x N.sub.y O.sub.z) to form a W/barrier/poly stack gate structure. The barrier layer blocks reaction between W and Si, enhances sheet resistance, enhances adhesion between the W and the poly, and is stable at high temperatures.

Abstract: A micromirror array fabricated on a semiconductor substrate 708. The micromirrors in the micromirror array logically divided into an interior active region 704 which selectively modulates light striking the mirrors in the interior active region 704, and an exterior border region 702 for producing a dark border around the image produced by the interior active region 704. A gap between each mirror allows adjacent mirrors to rotate. The gap 712 between mirrors in the interior active region 704 of the array is larger than the gap 710 between at least some of the mirrors in the exterior border region 702. The smaller gap 710 in the exterior region 702 is enabled by restricting mirrors in the exterior region 702 to a single direction of rotation.

Abstract: A method of operating a micromechanical device. The device is in a first state. Data for the next state of the device is loaded onto the activation circuitry of the device, where the next state may be the same state the device is currently in, or a state different from the first state. The equilibrium of the device is shifted away from the next state, by making the data appear complementary to the true data for the next state. When the trapping field is removed or lowered, and a signal to start the transition is provided, the device moves to its new state and the trapping field is reapplied. The data can be made to look complementary by either loading the complements to the true data, or by reversing the polarity of the trapping field.

Abstract: An etching apparatus (10) includes a process chamber (12) partially surrounded by an upper electrode (14) and a lower electrode (16). A semiconductor material (18) lies within the process chamber (12) and in contact with the lower electrode (16). The lower electrode (16) is connected to a first power supply (22) operating at a substantially high frequency and is also connected to a second power supply (24) operating at a relatively low frequency. The lower frequency of the second power supply (24) provides a degree of anisotropic control to the trench etching process performed on the semiconductor material (18). The added anisotropic control allows for the elimination of sidewall deposition enhancing materials within a plasma chemistry introduced into the process chamber (12) by a gas distributor (20).

Abstract: A method is disclosed for preventing formation of undesirable polysilicon word line gate filaments in integrated circuit devices such as VLSI dynamic random access memories employing field plate isolation. Before the word lines are processed, an oxide layer is formed in the field plate openings beneath sidewalls of nitride along the edges of the field plate openings. The oxide layer partially fills an undercut area beneath a dip out of the sidewall of nitride. The dip out of the sidewall of nitride is removed. The removal of the dip out and the partial filling of the undercut area reduces the possibility of polysilicon word line filaments from forming around the edge of the field plate openings in the undercut area when the word lines are later added. A field plate isolated memory device is also disclosed wherein along the edges of the field plate openings, the partially filling oxide layer and the sidewall nitride layer are approximately coincident.

Abstract: A void (60) is created in a semiconductor substrate (52) by forming a cavity which is subsequently filled with an organic polymer (66). The organic polymer is masked and etched to form a spacer. A dielectric (70) fills the portions of the cavity where the organic polymer was etched away. The organic polymer is subsequently etched leaving a void.

Abstract: A thin film etching process, wherein the rate of deposition of a robust sidewall passivant is controlled so that passivants can be continually deposited on the sidewalls of the resist pattern to change the geometry of the resist pattern during the processing step. That is, the existing pattern is modified as if a sidewall filament has been deposited on it, which can be advantageous for many purposes, without the added process complexity required by a sidewall filament process.

Abstract: A fluorine based metal etch chemistry, wherein an admixture of etch products (or species which are closely related to etch products) is added during the post etch stage, i.e. during the stage when the pattern has partially cleared by overetch is not yet completed, to maintain the balance of chemistries which provides selectivity and anisotropy. In a tungsten etch, WF.sub.6 is usefully added during the post etch period to provide this loading.

Abstract: An apparatus for reactive ion etching or plasma etching wherein the wafer faces downward. The process gas is supplied through a distributor which is below the wafer and has orifices pointing away from the wafer. The vacuum (exhaust) port is below the distributor, so that there is no bulk gas flow near the face of the wafer. Preferably transport of the process gasses and their products to the face of the wafer is dominated by diffusion.

Abstract: A complete integrated circuit processing module, wherein multiple processing stations, each with its own vacuum isolation, are located inside a single module which is held at hard vacuum. A wafer transport arm mechanism permits interchange of wafers among the processing stations and a load lock. The load lock is equipped to remove and replace wafers from a vacuum-sealed wafer carrier. The wafers remain face-down and under hard vacuum during all the wafer handling steps.

Abstract: An apparatus for reactive ion etching or plasma etching wherein the wafer faces downward. The process gas is supplied through a distributor which is below the wafer and has orifices pointing away from the wafer. The vacuum (exhaust) port is below the distributor, so that there is no bulk gas flow near the face of the wafer. Preferably transport of the process gasses and their products to the face of the wafer is dominated by diffusion.

Abstract: The disclosure relates to a two-step for selective anisotropic etching of polycrystalline silicon having a silicon dioxide base thereunder and an exposed opposing face with contaminants thereon including silicon dioxide without leaving a residue wherein the silicon is initially etched with a non-selective etchant for a distance below all contaminants and then an etchant used is a highly anisotropic selective polycrystalline silicon etchant.