Abstract: A method and apparatus for efficiently performing timing analysis on a circuit design. The present invention essentially provides a hybrid between a path enumeration algorithm and a critical path algorithm. As such, the present invention increases the number and degree of timing violations reported by a Critical Path Analysis (CPA) algorithm, while maintaining a performance advantage over a Path Enumeration (PE) algorithm. This is accomplished by providing a number of "pseudo" clocks to selected latches within the circuit design database, thereby tricking the CPA algorithm into reporting more timing violations than would otherwise be reported.

Abstract: In a system wherein a central computer complex is connected through central control modules (CCM) and channel modules (CM) to the control units of peripheral subsystems, a first queue is maintained in a CCM for Start I/O Fast (SIOF) commands waiting to be accepted by the CMs connected thereto. After a CM accepts an SIOF command and passes it on to a control unit, the control unit may return to the CM a busy status which is then passed through to the CCM. The CCM maintains a control unit busy (CUB) queue and an entry is made therein when busy status is returned. When a control unit reports control unit end status to the CCM, the CUB queue is linked to the top of the SIOF so that the CMs may again be informed that the SIOF commands are available. The arrangement avoids two interruptions of the central computer complex to report first that the control unit is busy and then that the control unit is available.

Abstract: An apparatus for and a method of Dynamic Subchannel Allocation permitting easily field modifiable assignment of Input/Output (I/O) subchannels to I/O channels. Many present day medium-to-large scale computers have an I/O unit(s) with a fixed number of I/O ports or I/O channels for the transmission of information between the computer and peripheral devices. Improvements to these I/O channels, now common in the art, permit multiple peripheral devices to be coupled to the computer through a single I/O channel. Each of these multiple peripheral devices may be said to communicate through an I/O subchannel. A given I/O subchannel designation logically specifies the hardware within the shared I/O channel that is dedicated to communication with the corresponding one of the multiple peripheral devices coupled to that shared I/O channel. The present invention is an improvement which provides for allocation of I/O subchannels to I/O channels in the field rather than at time of manufacture.