Abstract: A system and method for implementing integrated and adjustable image projection with auto-image correction in electronic devices using an in-facing or world-facing image projector are disclosed. A particular embodiment includes an electronic device including: a lid; a base including a hinge coupling the lid with the base; and an image projection subsystem including an image projector installed in the lid, the image projector being configured to produce a projected image that is projected onto a projection surface, the angle of the projection being adjustable by adjusting the angle of the lid relative to the base.

Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

Abstract: A system and method for implementing integrated and adjustable image projection with auto-image correction in electronic devices using an in-facing or world-facing image projector are disclosed. A particular embodiment includes an electronic device including: a lid; a base including a hinge coupling the lid with the base; and an image projection subsystem including an image projector installed in the lid, the image projector being configured to produce a projected image that is projected onto a projection surface, the angle of the projection being adjustable by adjusting the angle of the lid relative to the base.

Abstract: Systems and methods of supporting video streaming operations may involve transmitting a pulse width modulated (PWM) control signal to an imaging device, wherein the imaging devices identifies control data based on a duty cycle of the control signal. The imaging device can configure a video stream based on the control data and synchronize transmission of the video stream based on a frequency of the control signal.

Abstract: A system can include a host device and a remote terminal. The host device can include a host terminal, the host terminal including a host configuration manager to allocate a data lane to an I/O protocol and a protocol multiplexer to carry out allocation of the data lane based on the allocation of the configuration manager. The remote terminal can include a remote configuration manager. The remote configuration manager is to communicate with the remote configuration manager via a control bus to detect connection of an I/O device to an I/O port and to allocate the data lane to the I/O protocol.

Abstract: Systems and methods of supporting video streaming operations may involve transmitting a pulse width modulated (PWM) control signal to an imaging device, wherein the imaging devices identifies control data based on a duty cycle of the control signal. The imaging device can configure a video stream based on the control data and synchronize transmission of the video stream based on a frequency of the control signal.

Abstract: In one embodiment to reduce unwanted acoustic fan noise, the control signal for a computer system cooling fan is modulated so that the acoustic noise power spectral density of the fan has a bandwidth greater than when the control signal is constant.

Abstract: In one embodiment to reduce unwanted acoustic fan noise, the control signal for a computer system cooling fan is modulated so that the acoustic noise power spectral density of the fan has a bandwidth greater than when the control signal is constant.

Abstract: A method for variably providing an input signal includes receiving a set of complementary signals and a set of control signals. The method further includes outputting a selected one of a single-ended and a differential signal using at least one of the received complementary signals based, at least in part, on the received control signals.

Abstract: An apparatus includes a read clock path to provide a read clock signal to a memory controller, wherein the read clock signal is to control timing of a memory controller when reading from a memory. The apparatus also includes a write clock path, independent of the read clock path, to provide a write clock signal to the memory controller, wherein the write clock signal is to control timing of the memory controller when writing to the memory.

Abstract: An error-limiting circuit for regulating the time required to bring the output signal of a control system such as a phase-locked loop device into conformance with a reference input signal. For a phase-locked loop system the error-limiting circuit is a phase-error-limiting circuit that provides for a gradual changing of the signal frequency of a voltage-controlled oscillator of the phase-locked loop device so that frequency synchronization of subsequent devices coupled to the phase-locked loop with the reference signal is ensured. The phase-error-limiting circuit forms part of the phase-frequency detector that is coupled to a charge pump that outputs current to a loop filter that in turn effectively controls the voltage-controlled oscillator. The phase-error-limiting circuit acts to assert or de-assert as required an error-correcting UP or DOWN signal to the charge pump.

Abstract: A lock sensor circuit detects and indicates occurrence of a phase lock condition of an output signal of a phase lock loop (PLL) circuit when the PLL output signal is phase locked to a reference signal. A phase and frequency detector (PFD) has a reference signal input (REF IN) and a feedback signal input (VCO FBK IN) coupled to the output of the PLL circuit. The PFD delivers output UP and DOWN signals according to whether the reference signal leads or lags the feedback signal. A multi-bit up/down counter (FIG. 2 ) has UP and DOWN inputs coupled to the respective UP and DOWN outputs of the PFD and an m bit output (Q0, Q1, . . . Q10). A lock sensor circuit (50) coupled to the m bit up/down counter monitors the nth bit output (QN) of the up/down counter where n<m. A first down counter (F1, F2) counts consecutive output DOWN signals in the absence of an output UP signal. A second up counter (F3, F4) counts consecutive output UP signals in the absence of an output DOWN signal.

Abstract: A FAST OE signal circuit generates FAST OE signals of high and low potential levels. A SLOW OE signal circuit generates SLOW OE signals corresponding to FAST OE signals. The SLOW OE signals have the same high or low potential level as the corresponding FAST OE signals and occur a specified time delay after the corresponding FAST OE signals. A tristate output buffer circuit operates in the bistate mode when enabled by high potential level OE signals for transmitting binary data signals, and operates in a high Z tristate mode when disabled by low potential level OE signals. The FAST OE signal circuit and SLOW OE signal circuit ae coupled in parallel to the tristate output buffer circuit for enabling and disabling the tristate output buffer circuit. The FAST and SLOW OE signals in combination skew the enable time relative to the disable time.