Patents by Inventor Duane Galbi
Duane Galbi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230325265Abstract: A network interface device connects to one or more endpoint devices and a network. The network interface device receives packet from the network and parses the packet to determine characteristics of the packet, where the packet includes serialized data according to a serialization format. Based on the characteristics, the network interface device determines whether data within the packet can be deserialized using data transformation acceleration hardware provided on the network interface device and which of a plurality of sub-protocols of a multiprotocol interconnect are to be utilized to transport the data to a destination device in the one or more endpoint devices.Type: ApplicationFiled: June 13, 2023Publication date: October 12, 2023Inventors: Susanne M. Balle, Duane Galbi, Shihwei Roger Chien, Nagabhushan Chitlur, Andrzej Kuriata
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Publication number: 20230185658Abstract: An example of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to a memory for a range of addresses within a memory address space, configure a first region of the memory within a first sub-range of addresses within the memory address space to be accessed with a first protection level of two or more memory fault protection levels, and configure a second region of the memory within a second sub-range of addresses within the memory address space that is non-overlapping with the first sub-range to be accessed with a second protection level of the two or more memory fault protection levels. Other examples are disclosed and claimed.Type: ApplicationFiled: February 10, 2023Publication date: June 15, 2023Applicant: Intel CorporationInventors: Duane Galbi, Matthew Adiletta
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Publication number: 20230096451Abstract: Techniques for remote disaggregated infrastructure processing units (IPUs) are described. An apparatus described herein includes an interconnect controller to receive a transaction layer packet (TLP) from a host compute node; identify a sender and a destination from the TLP; and provide, to a content addressable memory (CAM), a key determined from the sender and the destination. The apparatus as described herein can further include core circuitry communicably coupled to the interconnect controller, the core circuitry to determine an output of the CAM based on the key, the output comprising a network address of an infrastructure processing unit (IPU) assigned to the host compute node, wherein the IPU is disaggregated from the host compute node over a network; and send the TLP to the IPU using a transport protocol.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Applicant: Intel CorporationInventors: Salma Johnson, Duane Galbi, Bradley Burres, Jose Niell, Jeongnim Kim, Reshma Lal, Anandhi Jayakumar, Mrittika Ganguli, Thomas Willis
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Publication number: 20230029026Abstract: A network processing device connects to one or more devices in a computing node and connects to one or more other network processing devices of other computing nodes. The network processing device identifies a policy for allowing devices in other computing nodes to access a particular resource of one of the devices in its computing node. The network processing device receives an access request to access the particular resource from another network processing device and sends a request to the device hosting the particular resource based on the access request and the policy.Type: ApplicationFiled: September 30, 2022Publication date: January 26, 2023Applicant: Intel CorporationInventors: Francesc Guim Bernat, Karthik Kumar, Susanne M. Balle, Andrzej Kuriata, Duane Galbi
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Patent number: 10884968Abstract: Technologies for flexible I/O protocol acceleration include a computing device having a root complex, a smart endpoint coupled to the root complex, and an offload complex coupled to the smart endpoint. The smart endpoint receives an I/O transaction that originates from the root complex and parses the I/O transaction based on an I/O protocol and identifies an I/O command. The smart endpoint may parse the I/O transaction based on endpoint firmware that may be programmed by the computing device. The smart endpoint accelerates the I/O command and provides a smart context to the offload complex. The smart endpoint may copy the I/O command to memory of the smart endpoint or the offload complex. The smart endpoint may identify protocol data based on the I/O command and copy the protocol data to the memory of the smart endpoint or the offload complex. Other embodiments are described and claimed.Type: GrantFiled: March 27, 2019Date of Patent: January 5, 2021Assignee: Intel CorporationInventors: Matthew J. Adiletta, Bradley Burres, Duane Galbi, Amit Kumar, Yadong Li, Salma Mirza, Jose Niell, Thomas E. Willis, William Duggan
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Patent number: 10783100Abstract: Technologies for flexible I/O endpoint acceleration include a computing device having a root complex, a soft endpoint coupled to the root complex, and an offload complex coupled to the soft endpoint. The soft endpoint establishes an emulated endpoint hierarchy based on endpoint firmware. The computing device may program the endpoint firmware. The soft endpoint receives an I/O transaction that originates from the root complex and determines whether to process the I/O transaction. The soft endpoint may process the I/O transaction or forward the I/O transaction to the offload complex. The soft endpoint may encapsulate the I/O transaction with metadata and forward the encapsulated transaction to the offload complex. The soft endpoint may store responses from the offload complex in a history buffer and retrieve the responses in response to retried I/O transactions. The I/O transaction may be a PCI Express transaction layer packet. Other embodiments are described and claimed.Type: GrantFiled: March 27, 2019Date of Patent: September 22, 2020Assignee: Intel CorporationInventors: Matthew J. Adiletta, Brad Burres, Duane Galbi, Amit Kumar, Yadong Li, Salma Mirza, Jose Niell, Thomas E. Willis, William Duggan
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Publication number: 20200073846Abstract: Technologies for flexible I/O protocol acceleration include a computing device having a root complex, a smart endpoint coupled to the root complex, and an offload complex coupled to the smart endpoint. The smart endpoint receives an I/O transaction that originates from the root complex and parses the I/O transaction based on an I/O protocol and identifies an I/O command. The smart endpoint may parse the I/O transaction based on endpoint firmware that may be programmed by the computing device. The smart endpoint accelerates the I/O command and provides a smart context to the offload complex. The smart endpoint may copy the I/O command to memory of the smart endpoint or the offload complex. The smart endpoint may identify protocol data based on the I/O command and copy the protocol data to the memory of the smart endpoint or the offload complex. Other embodiments are described and claimed.Type: ApplicationFiled: March 27, 2019Publication date: March 5, 2020Inventors: Matthew J. Adiletta, Bradley Burres, Duane Galbi, Amit Kumar, Yadong Li, Salma Mizra, Jose Niell, Thomas E. Willis, William Duggan
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Publication number: 20200065271Abstract: Technologies for flexible I/O endpoint acceleration include a computing device having a root complex, a soft endpoint coupled to the root complex, and an offload complex coupled to the soft endpoint. The soft endpoint establishes an emulated endpoint hierarchy based on endpoint firmware. The computing device may program the endpoint firmware. The soft endpoint receives an I/O transaction that originates from the root complex and determines whether to process the I/O transaction. The soft endpoint may process the I/O transaction or forward the I/O transaction to the offload complex. The soft endpoint may encapsulate the I/O transaction with metadata and forward the encapsulated transaction to the offload complex. The soft endpoint may store responses from the offload complex in a history buffer and retrieve the responses in response to retried I/O transactions. The I/O transaction may be a PCI Express transaction layer packet. Other embodiments are described and claimed.Type: ApplicationFiled: March 27, 2019Publication date: February 27, 2020Inventors: Matthew J. Adiletta, Brad Burres, Duane Galbi, Amit Kumar, Yadong Li, Salma Mirza, Jose Niell, Thomas E. Willis, William Duggan
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Publication number: 20070168768Abstract: Methods and apparatus for performing error correction code (ECC) coding techniques for high-speed implementations. The ECC code word is structured to facilitate a very fast single-error-detect (SED) that allows state machines to be stopped within a single cycle when an error is detected and enables a corresponding single-error-correct (SEC) operation to be performed over multiple cycles while the state machines are in a suspended mode.Type: ApplicationFiled: November 21, 2005Publication date: July 19, 2007Inventors: Duane Galbi, Ranjit Loboprabhu, Jose Niell
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Publication number: 20070006012Abstract: In general, in one aspect, the disclosure describes an apparatus for engineering di/dt. The apparatus includes a plurality of functional blocks to perform different functions. The apparatus also includes a clock source to provide a clock signal to said plurality of functional blocks. At least one gating device is used to regulate application of the clock to the plurality of functional blocks. A controller is included to control the at least one gating device and turning-on of the clock signal.Type: ApplicationFiled: June 29, 2005Publication date: January 4, 2007Inventors: Praveen Mosur, Duane Galbi, Benjamin Cahill
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Patent number: 6366502Abstract: Circuitry for reading from and writing to memory cells of a group of memory cells. The circuitry comprises read circuitry and write circuitry each connectable to bit lines associated with respective ones of the memory cells. The read circuitry is arranged to read from the cells and the write circuitry is arranged to write to the cells. Wherein the read circuitry and write circuitry are configured so that more cells in the group can be simultaneously written to during a write operation than can be simultaneously read from during a read operation.Type: GrantFiled: June 5, 2000Date of Patent: April 2, 2002Assignee: STMicroelectronics LimitedInventors: Steven Charles Docker, Duane Galbi
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Patent number: 5847575Abstract: A driver circuit for limiting electrical noise on a quiescent signal is provided which includes a Transition High Driver circuit, a Transition Low Driver circuit, a Quiescent High Driver circuit, and a Quiescent Low Driver circuit. The driver circuit comprises means for driving an electrical signal with a presumed noisy Transition Power Supply network while it is transitioning from a low voltage level to a high voltage level or vice versa. The signal is driven by the Transition Power Supply network until the electrical signal reaches its quiescent voltage level. At this time, the signal is no longer driven by the Transition Power Supply network but rather by a presumed clean Quiescent Power Supply network. In this manner, noise from transitioning signals is prevented from coupling onto quiescent signals.Type: GrantFiled: June 21, 1996Date of Patent: December 8, 1998Assignee: Digital Equipment CorporationInventors: Duane Galbi, Chris L. Houghton, John A. Kowaleski, Jr.
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Patent number: 5547894Abstract: A method of processing CMOS circuits provides up to three types of transistors (standard NFETs, PFETs and high current NFETs) without additional masking steps by the simultaneous implantation of the standard PFET and the high current NFET low doped source and drain implants and a separate implantation of the standard NFET.Type: GrantFiled: December 21, 1995Date of Patent: August 20, 1996Assignee: International Business Machines CorporationInventors: Jack A. Mandelman, Duane Galbi, James A. Slinkman, William R. Tonti