Abstract: A random access memory system having at least four independent access ports. In the preferred mode, a random access memory core is accessible by two independent read ports and two independent write ports. The four ports can separately and simultaneously access the same or different addressable locations within the random access memory core, except for collision conditions. A collision condition occurs whenever more than one write ports attempt to simultaneously write into the same addressable location. Such a simultaneous write access to the same cell could produce a metastable condition wherein the data storage state is indeterminate. Collision conditions result in the aborting of at least one of the write accesses on a priority basis. The abort function also protects the hardware from short circuit.