Abstract: The integrated, multiple independent, simultaneous signal software defined radio system architecture of this invention is suitable for many new very-low latency, software defined radio applications, both cognitive and conventional, including: communications networks, electronic warfare, surveillance and radar. The system supports multiple operations, locally controlled or remotely controlled, with simultaneous signals prosecutions and anti-jam system-to-system networking. New cognitive waveforms are defined that simultaneously seek to maximize data throughput in arbitrary spectral environments, while normally avoiding interference with current and new arbitrary signal occurrences.

Abstract: A tailored response cascaded integrator comb digital filter is disclosed which has a cascaded integrator structure, a cascaded comb structure, a first rate change component, a second rate change component and can additionally include a resonator. The improved structure achieves greater bandwidth without requiring higher sampling rates. In an additional embodiment, a pre-decimated cascaded integrator filter section for a cascaded integrator comb digital filter is disclosed as having a data rate change component and a first integrator structure receiving data at the rate established by the data rate change component and modifying the received data. The pre-decimated filter section can also include a second integration structure. The pre-decimate structure outputs data equivalent to data that would be output by a post-decimated cascaded integrator structure having an equal number of cascaded integrator stages.

Abstract: Multi-bit, monotonic quantizer and linearized delta-sigma modulator based analog-to-digital converter (ADC) modulators and digital-to-analog converter (DAC) modulators are disclosed. A folded monotonic quantizer provides tri-state to bi-state mapping such that three state bits may be utilized but are not required to be transported and stored. The multi-bit ADC and DAC modulators provide linearized, spurious free outputs that require less power and utilize lower oversampling ratios to provide wider bandwidths at high-performance, spurious-free dynamic ranges, making them ideally suitable for use in direct sampling receivers and direct digital transmitters.

Abstract: A status phase processor for a data pattern recognizer or correlator provides an optimized synchronization signal. The synchronization signal can be utilized to adjust the data sampling clock. The data pattern correlator utilizes two or more samples per symbol of the signal which is expected to be received. The system provides high accuracy correlation without significant hardware and software overhead. The status phase processor relies on a counter circuit and a logic circuit for generating the synchronization signal.

Abstract: A data pattern recognizer or correlator provides an optimized synchronization signal. The data pattern correlator utilizes two or more samples per bit of the signal which is expected to be received. The system provides high accuracy correlation without significant hardware and software overhead. The two or more samples are adjacent samples. The correlator can be used in any communication system, including a modem, a radio, a transceiver, a satellite, or other system where data patterns are detected.

Abstract: A high pass delta-sigma modulator apparatus is disclosed for use in analog-to-digital and digital-to-analog converters. The apparatus includes a signal input, a differentiator component, a signal transducer producing an output signal, an inverse signal transducer producing an input compatible feedback signal, and a feedback loop coupling a feedback signal back to said differentiator component. Also disclosed is a Nyquist response restoring delta-sigma modulator based analog-to-digital and digital-to-analog converter apparatus having a first modulator set, a first scaling component, a second modulator set and a post processing combiner. In the various embodiments, the modulator sets can include an analog signal input, a digital signal input, a quantizer, a digital resolution rounder, a digital resolution truncator, a digital-to-analog signal transducer, a digital resolution expander, a delta sigma modulator structure, a feedback structure, an analog signal output, and one or more digital signal outputs.

Abstract: A multi-band direct sampling receiver is described. The multi-band direct sampling receiver of the present invention is based upon state-of-the-art, very high speed integrated circuit and digital signal processing. As such, the performance of the direct sampling receiver of the present invention contemplates improvements in large, very high-speed integrated circuits. The direct sampling receiver of the present invention contemplates large scale integration and very large scale integration techniques.

Abstract: A sigma-delta low-pass/band-pass based modulator for analog-to-digital converters includes at least one or more tunable band-pass filter stages. The filter stages are configured arrays with one or more parallel filter stages arranged as a group, and with one or more groups in cascade. The input signal is provided to all filter stages in the first group, and the outputs of the last group are combined and provided to the output processing elements. The output processing elements provide the signal conversion to the converter output, as well as the inverse conversion of the output signal to form the feedback signal or signals. All filter stages receive a feedback signal from the output processing elements. Each of the tunable band-pass filter stages is independently tunable to a respective predetermined frequency. At least one of the filter stages can be configured to support low-pass operation in conjunction with band-pass operation for increased low-pass signal bandwidth.

Abstract: A multi-mode, multi-band, multi-user radio system architecture includes four channels of exciter circuits and receiver circuits coupled to a digital signal processing array. Each of the exciter and receiver circuits includes three separate signal paths for three separate frequency ranges of analog signals. Each path includes an analog-to-digital converter or a digital-to-analog converter for converting both modulated analog signals to modulated digital signals and modulated digital signals to modulated analog signals. The digital signal processing array performs modulation and demodulation functions for the radio system.

Abstract: A sigma-delta-sigma modulator for analog-to-digital and digital-to-analog converters is described. The sigma-delta-sigma modulator is amenable to fabrication of high speed LSI and VLSI digital components for fixed and programmable processes for minimizing and eliminating required analog circuitry in a digital radio. The sigma-delta-sigma modulator is utilized in a direct sampling receiver in which the received RF is converted by high resolution analog-to-digital processing and subsequently translated to baseband, filtered and demodulated completely in the digital domain. The modulator is also utilized in a direct digital transmitter in which the baseband modulation is formed, translated to RF, and converted to analog by high resolution digital-to-analog processing completely in the digital domain.

Abstract: A composite signal recognizer, separator, and FM demodulator apparatus for processing received radio signals. The receiver utilizes N demodulators to process a received signal, where N is equal to or greater than the number of co-channel signals or perceived interference. Detailed in both cross-coupled and cascaded fashion, the receiver first tracks to a predominant (stronger) signal, and regeneratively improves track on other (weaker) signals by subtracting the predominant signal or the predominant noise portion from the input of further demodulation stages.

Abstract: A composite signal recognizer separator, and PSK, AM, FM demodulator apparatus for processing received communication signals. The receiver utilizes N demodulators cascadely-coupled, where N is equal to or greater than the number of co-channel signals or perceived interference. Detailed in both dual and single stages cascaded fashion, the receiver first tracks to a predominant (stronger) signal, and regeneratively improves track on other (weaker) signals by subtracting predominant noise portion from the input of further demodulation stages. A unified approach to PSK carrier phase tracking, character data tracking, and recovery clock tracking is utilized.

Abstract: The outputs of two like frequency oscillators are combined to form a single reliable clock signal, with one oscillator functioning as a slave under the control of the other to achieve phase coincidence when the master is operative and in a free-running mode when the master is inoperative so that failure of either oscillator produces no effect on the clock signal.