Abstract: A dynamic random access memory (DRAM) includes a bit line pair, including a first bit line and a second bit line. Memory cells and a sense amplifier are coupled to the bit lines. A first characterization cell is coupled between the first bit line and a first reference supply line. The first characterization cell includes a capacitor. Similarly, a second characterization cell is coupled between the first bit line and the first reference supply line. The second characterization cell also includes a capacitor but preferably with a different capacitance. In the preferred embodiment, similar characterization cells are coupled to the second bit line.

Abstract: An apparatus and method is provided that reduces the propagation delay in a conductor carrying an electrical signal from a first area of a circuit to a second area of the circuit. The conductor is fabricated to include a first conductor extending from the first area to the second area. The conductor also includes a second conductor extending substantially parallel and along the first conductor and electrically connected to the first conductor. A third and additional conductors may also be used which extend substantially parallel and along the first conductor and are electrically connected to the first conductor. The additional second conductor (and any additional conductors) reduces the capacitance of the conductor thereby reducing the propagation delay in the conductor (increasing the speed of the signal). The additional conductor(s) effectively “shield” the first conductor from some capacitance that the first conductor would normally “see” without the use of such additional conductors.