Patents by Inventor Duane M. Goodner

Duane M. Goodner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9236427
    Abstract: Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. A first capacitor electrode is formed within the opening and has sidewalls along the protective material. At least some of the silicon-containing mass is removed with an etch. The protective material protects the first capacitor electrode from being removed by the etch. A second capacitor electrode is formed along the sidewalls of the first capacitor electrode, and is spaced from the first capacitor electrode by capacitor dielectric. Some embodiments include multi-material structures having one or more of aluminum nitride, molybdenum nitride, niobium nitride, niobium oxide, silicon dioxide, tantalum nitride and tantalum oxide. Some embodiments include semiconductor constructions.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: January 12, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Joseph Neil Greeley, Duane M. Goodner, Vishwanath Bhat, Vassil N. Antonov, Prashant Raghu
  • Publication number: 20150303147
    Abstract: Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions.
    Type: Application
    Filed: June 26, 2015
    Publication date: October 22, 2015
    Inventors: Jaydeb Goswami, Hung Ming Tsai, Duane M. Goodner
  • Patent number: 9099472
    Abstract: Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: August 4, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jaydeb Goswami, Hung Ming Tsai, Duane M. Goodner
  • Publication number: 20150054127
    Abstract: Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. A first capacitor electrode is formed within the opening and has sidewalls along the protective material. At least some of the silicon-containing mass is removed with an etch. The protective material protects the first capacitor electrode from being removed by the etch. A second capacitor electrode is formed along the sidewalls of the first capacitor electrode, and is spaced from the first capacitor electrode by capacitor dielectric. Some embodiments include multi-material structures having one or more of aluminum nitride, molybdenum nitride, niobium nitride, niobium oxide, silicon dioxide, tantalum nitride and tantalum oxide. Some embodiments include semiconductor constructions.
    Type: Application
    Filed: September 30, 2014
    Publication date: February 26, 2015
    Inventors: Joseph Neil Greeley, Duane M. Goodner, Vishwanath Bhat, Vassil N. Antonov, Prashant Raghu
  • Patent number: 8865544
    Abstract: Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. A first capacitor electrode is formed within the opening and has sidewalls along the protective material. At least some of the silicon-containing mass is removed with an etch. The protective material protects the first capacitor electrode from being removed by the etch. A second capacitor electrode is formed along the sidewalls of the first capacitor electrode, and is spaced from the first capacitor electrode by capacitor dielectric. Some embodiments include multi-material structures having one or more of aluminum nitride, molybdenum nitride, niobium nitride, niobium oxide, silicon dioxide, tantalum nitride and tantalum oxide. Some embodiments include semiconductor constructions.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: October 21, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Joseph Neil Greeley, Duane M. Goodner, Vishwanath Bhat, Vassil N. Antonov, Prashant Raghu
  • Patent number: 8766347
    Abstract: Some embodiments include capacitors. The capacitors may include container-shaped storage node structures that have, along a cross-section, a pair of upwardly-extending sidewalls. Individual sidewalls may have a narrower segment over a wider segment. Capacitor dielectric material and capacitor electrode material may be along the narrower and wider segments of the sidewalls. Some embodiments include methods of forming capacitors in which an initial container-shaped storage node structure is formed to have a pair of upwardly-extending sidewalls along a cross-section, with the sidewalls being of thickness that is substantially constant or increasing from a base to a top of the initial structure. The initial structure is then converted into a modified storage node structure by reducing thicknesses of upper segments of the sidewalls while leaving thicknesses of lower segments of the sidewalls substantially unchanged.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: July 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Duane M. Goodner, Sanjeev Sapra, Darwin Franseda Fan
  • Publication number: 20140048943
    Abstract: Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions.
    Type: Application
    Filed: October 25, 2013
    Publication date: February 20, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Jaydeb Goswami, Hung Ming Tsai, Duane M. Goodner
  • Publication number: 20140015097
    Abstract: Some embodiments include a method of forming a capacitor. An opening is formed through a silicon-containing mass to a base, and sidewalls of the opening are lined with protective material. A first capacitor electrode is formed within the opening and has sidewalls along the protective material. At least some of the silicon-containing mass is removed with an etch. The protective material protects the first capacitor electrode from being removed by the etch. A second capacitor electrode is formed along the sidewalls of the first capacitor electrode, and is spaced from the first capacitor electrode by capacitor dielectric. Some embodiments include multi-material structures having one or more of aluminum nitride, molybdenum nitride, niobium nitride, niobium oxide, silicon dioxide, tantalum nitride and tantalum oxide. Some embodiments include semiconductor constructions.
    Type: Application
    Filed: July 11, 2012
    Publication date: January 16, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Joseph Neil Greeley, Duane M. Goodner, Vishwanath Bhat, Vassil N. Antonov, Prashant Raghu
  • Patent number: 8592985
    Abstract: Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: November 26, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Jaydeb Goswami, Hung Ming Tsai, Duane M. Goodner
  • Publication number: 20130264713
    Abstract: Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 10, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Jaydeb Goswami, Hung Ming Tsai, Duane M. Goodner
  • Publication number: 20120326275
    Abstract: Some embodiments include capacitors. The capacitors may include container-shaped storage node structures that have, along a cross-section, a pair of upwardly-extending sidewalls. Individual sidewalls may have a narrower segment over a wider segment. Capacitor dielectric material and capacitor electrode material may be along the narrower and wider segments of the sidewalls. Some embodiments include methods of forming capacitors in which an initial container-shaped storage node structure is formed to have a pair of upwardly-extending sidewalls along a cross-section, with the sidewalls being of thickness that is substantially constant or increasing from a base to a top of the initial structure. The initial structure is then converted into a modified storage node structure by reducing thicknesses of upper segments of the sidewalls while leaving thicknesses of lower segments of the sidewalls substantially unchanged.
    Type: Application
    Filed: September 7, 2012
    Publication date: December 27, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Duane M. Goodner, Sanjeev Sapra, Darwin Franseda Fan
  • Patent number: 8283236
    Abstract: Some embodiments include capacitors. The capacitors may include container-shaped storage node structures that have, along a cross-section, a pair of upwardly-extending sidewalls. Individual sidewalls may have a narrower segment over a wider segment. Capacitor dielectric material and capacitor electrode material may be along the narrower and wider segments of the sidewalls. Some embodiments include methods of forming capacitors in which an initial container-shaped storage node structure is formed to have a pair of upwardly-extending sidewalls along a cross-section, with the sidewalls being of thickness that is substantially constant or increasing from a base to a top of the initial structure. The initial structure is then converted into a modified storage node structure by reducing thicknesses of upper segments of the sidewalls while leaving thicknesses of lower segments of the sidewalls substantially unchanged.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: October 9, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Duane M. Goodner, Sanjeev Sapra, Darwin Franseda Fan
  • Publication number: 20120187533
    Abstract: Some embodiments include capacitors. The capacitors may include container-shaped storage node structures that have, along a cross-section, a pair of upwardly-extending sidewalls. Individual sidewalls may have a narrower segment over a wider segment. Capacitor dielectric material and capacitor electrode material may be along the narrower and wider segments of the sidewalls. Some embodiments include methods of forming capacitors in which an initial container-shaped storage node structure is formed to have a pair of upwardly-extending sidewalls along a cross-section, with the sidewalls being of thickness that is substantially constant or increasing from a base to a top of the initial structure. The initial structure is then converted into a modified storage node structure by reducing thicknesses of upper segments of the sidewalls while leaving thicknesses of lower segments of the sidewalls substantially unchanged.
    Type: Application
    Filed: January 20, 2011
    Publication date: July 26, 2012
    Applicant: Micron Technology, Inc.
    Inventors: Duane M. Goodner, Sanjeev Sapra, Darwin Franseda Fan