Abstract: The clock configuration of a printed circuit board (PCB) processor card is described. A processor card including a processor, its associated processor card system bus, a clock generator, and its associated processor card system clock bus is optimized by providing various clock configurations and distributions. In one configuration, multiple clock signals are coupled to a system clock bus for distributing to a host card having system devices. In another configuration, multiple clock signals having various clock rates are coupled to the processor device on the processor card.

Abstract: The present invention is a printed circuit board having conductive layers split into electrically isolated voltage supply plane regions each plane region being connectable to an external supply voltage. The voltage supply plane regions are split to reduce the total number of PCB conductive layers. Voltage supply plane regions are configured to match the device voltage requirements and their placement on the PCB. In the case in which a circuit includes a device having two voltage supply requirements, a first set of the device's power supply pins are fixedly coupled to a first voltage supply plane region and a second set of the device's power supply pins are fixedly coupled to a second voltage supply plane region. In this instance, each of the first and second voltage supply plane regions are fixedly connectable to external voltage supplies or to a voltage regulator according to the voltage supply requirements of the device.

Abstract: A method of designing improved CMOS input circuits by understanding and selecting appropriate drive strength for a CMOS output from a previous stage. The method involves modeling the net using HSPICE and including a transit time term to accurately model charge storage, then size drivers as needed to keep the V.sub.ss clamps out of forward conduction. Excessive ringing can cause data errors in the input stage if unterminated, falling edge transitions in such a net can turn on a receiver's V.sub.ss clamp diode (stored charge in the V.sub.ss clamp diode combined with the line's inductance and the receiver's capacitance form an energized resonant circuit which can release energy at a time to cause a data glitch). Currently, XNS simulation miscalculates the ring amplitude by a factor of three. Driver scaling and termination can eliminate the problem by keeping the receiver's V.sub.ss clamp out of forward conduction. Driver sizing can control the problem.

Abstract: A printed circuit board (PCB) processor card is described. The processor card includes a processor, its associated processor card system bus, a clock generator, and its associated processor card system clock bus. The processor card is designed to include the elements that are most likely to be upgraded, i.e. the processor and the clock. As such it is particularly useful when employed for system upgrades.

Abstract: The present invention is a printed circuit board design having a configurable voltage supply and a method for implementing a configurable voltage supply PCB with a family of circuit designs. The printed circuit board is designed such that voltage supply planes can be configured to match the device requirements for different ICs inserted into the PCB. The PCB comprises electrically isolated conductive layers that are split into a plurality of electrically isolated fixed and undefined voltage planes. The fixed voltage planes are each coupled to a different supply voltage provided by an external power supply. Undefined voltage planes are coupled to fixed voltage planes with insertable conductive jumpers to obtain the desired voltage supply for each voltage plane. The voltage plane configuration of a particular PCB can be changed depending on where jumpers are inserted to accommodate device voltage requirements over a family of devices.