Abstract: A system and method to determine the operating status of an electrical system includes a system controller and an actuator controller. The system controller determines if the actuator controller is operating properly and initiates a safe mode of operation if the actuator is not operating properly. In turn, the actuator controller determines if the system controller is operating properly and initiates a safe mode of operation if the system controller is not operating properly.

Abstract: A system and method to determine the operating status of an electrical system includes a system controller and an actuator controller. The system controller determines if the actuator controller is operating properly and initiates a safe mode of operation if the actuator is not operating properly. In turn, the actuator controller determines if the system controller is operating properly and initiates a safe mode of operation if the system controller is not operating properly.

Abstract: A non-volatile memory including a plurality of memory cells configured to store data and a plurality of redundant memory cells configured to be used for functionally replacing defective memory cells. The memory further includes a protection register comprising storage elements configured to store configuration data of the memory device. The storage elements of the protection register are redundant memory cells not being used to replace defective memory cells.

Abstract: A non-volatile memory including a plurality of memory cells configured to store data and a plurality of redundant memory cells configured to be used for functionally replacing defective memory cells. The memory further includes a protection register comprising storage elements configured to store configuration data of the memory device. The storage elements of the protection register are redundant memory cells not being used to replace defective memory cells.

Abstract: In a flash EEPROM memory array in which a plurality of floating gate field effect transistor memory devices are arranged in rows and columns, in which wordlines are utilized to select rows of such devices and bitlines are utilized to select columns of such devices, in which groups of such devices are arranged in blocks which are independently erasable, and the blocks are divided into sub-blocks for storing lower and upper bytes of words to be stored, apparatus is provided for disabling the wordlines to all high byte sub-blocks when a low byte sub-block is to be programmed, for disabling the wordlines to all low byte sub-blocks when a high byte sub-block is to be programmed, for grounding the sources of all high byte sub-blocks when a low byte sub-block is to be programmed, and for grounding the sources of all low byte sub-blocks when a high byte sub-block is to be programmed.