Abstract: In preferred embodiments, a system including a transmitter, a receiver, and a serial link, in which the transmitter is configured to transmit video data, embedded-clock auxiliary data (or auxiliary data derived from embedded-clock auxiliary data), and a video clock over the link to the receiver. The transmitter is configured to extract a sample clock from the auxiliary data without use of a phase-locked loop, and to generate time stamp data in response to the sample clock and the video clock. Typically, the auxiliary data are SPDIF (or other) audio data, and the sample clock changes state in response to codes that occur periodically in the audio data. Other aspects of the invention are a transmitter for use in such a system, a time stamp data generation circuit for use in such a transmitter, and a method for generating time stamp data in response to a stream of embedded-clock auxiliary data and a video clock.

Abstract: A communication system including a transmitter, a receiver, and a serial link, in which encoded data (e.g., video, audio, and optionally also other auxiliary data) are transmitted from the transmitter to the receiver. The serial link can but need not be a TMDS or TMDS-like link. In typical embodiments, packets of encoded audio data are transmitted over each of one or more channels of the link during data islands between bursts of encoded video data, a pixel clock is transmitted over the link, and the receiver regenerates a clock for the audio data using time code data in the packets and the pixel clock. Other aspects of the invention are transmitters for transmitting encoded data and a pixel clock over a serial link, receivers for receiving such data and pixel clock and performing audio clock regeneration, and methods for transmitting encoded data and a pixel clock over a serial link and performing clock regeneration using the transmitted data and pixel clock.

Abstract: A communication system including a transmitter, a receiver, and a serial link, in which encoded data (e.g., video, audio, and optionally also other auxiliary data) are transmitted from the transmitter to the receiver. The serial link can but need not be a TMDS or TMDS-like link. In typical embodiments, packets of encoded audio data are transmitted over each of one or more channels of the link during data islands between bursts of encoded video data. Other aspects of the invention are transmitters for use in encoding data for transmission over a serial link, receivers for receiving such data, and methods for sending encoded data over a serial link.

Abstract: In preferred embodiments, a system including a transmitter, a receiver, and a serial link, in which the transmitter is configured to transmit video data, embedded-clock auxiliary data (or auxiliary data derived from embedded-clock auxiliary data), and a video clock over the link to the receiver. The transmitter is configured to extract a sample clock from the auxiliary data without use of a phase-locked loop, and to generate time stamp data in response to the sample clock and the video clock. Typically, the auxiliary data are SPDIF (or other) audio data, and the sample clock changes state in response to codes that occur periodically in the audio data. Other aspects of the invention are a transmitter for use in such a system, a time stamp data generation circuit for use in such a transmitter, and a method for generating time stamp data in response to a stream of embedded-clock auxiliary data and a video clock.

Abstract: A method and system for establishing intensity levels for sub-pixels of a display device with overlapping logical pixels. The dithering system combines frame rate control techniques with contributions from overlapping pixels to establish the intensity level of each sub-pixel. The dithering system initially provides an assignment of frame numbers to each sub-pixel. The dithering system then receives a logical pixel color that includes an intensity value for each component color (e.g., red, green, and blue) for each logical pixel. The dithering system maps each component intensity value of each logical pixel to an intensity value with a low depth plus a remainder. The dithering system generates a sub-pixel intensity value for each sub-pixel of each logical pixel using frame rate control to adjust the intensity value of each sub-pixel based on the remainder and current frame number.

Abstract: An array includes redundant integrated scan drivers that can provide signals to each other through scan lines. Each scan driver can be a shift register, each stage of which includes a tri-state inverter to provide its output to one of the scan lines. To transfer signals from one shift register to the other, one shift register provides signals while the outputs of the other shift register are in a floating state. The other shift register receives the signals and can then shift them to its output. The signals can be test signals used to detect defects in the shift registers and in the array. Also, each stage in each shift register is connected to receive signals from the scan line that is driven by the preceding stage. Therefore, if the preceding stage is removed due to a defect, the following stage can receive signals through the scan line from the other shift register and continue to function even though its preceding stage is removed.