Abstract: Error detecting and correcting operations for a plurality of input bits comprised of input data bits and associated check bits are implemented using two IC chips in order to overcome chip output limitations. The use of two identical IC chips for this purpose is made possible by employing a specially chosen inversely symmetrical Hamming code and by wiring the input data bits and the input check bits in an inverse manner with respect to the input terminals of the two IC chips. As a result, even though each IC chip performs the same error detecting and correcting operations, it does so inversely with respect to the input data bits and the input check bits so that each IC chip is able to provide one-half of the required output bits.

Abstract: Error detecting and correcting operations for a plurality of input bits comprised of input data bits and associated check bits are implemented using two IC chips in order to overcome chip output limitations. In addition, redundancies derived from the use of two IC chips are employed to provide automatic self-checking of the detecting operation of each chip. The use of two identical IC chips for this purpose is made possible by employing a specially chosen inversely symmetrical Hamming code and by wiring the input data bits and the input check bits in an inverse manner with respect to the input terminals of the two IC chips. As a result, even though each IC chip performs the same error detecting and correcting operations, it does so inversely with respect to the input data bits and the input check bits so that each IC chip is able to provide one-half of the required output bits.

Abstract: A method employing two identical IC chips for providing error detecting and correcting operations on a plurality of input bits comprised of input data bits and input check bits, wherein a single one of the IC chips has an insufficient number of available outputs to provide all of the required outputs. The method includes applying the input data bits and the input check bits to the input terminals of each IC chip in an inverse manner relative to one another, and then performing the error detecting and correcting operations on each chip in accordance with an inversely symmetrical Hamming code. As a result, even though the same detecting and correcting operations are performed on each IC chip, they are performed in an inverse manner with respect to the input data and input check bits so that each IC chip is able to provide one-half of the required output bits.

Abstract: A method employing two identical IC chips for providing error detecting and correcting operations on a plurality of input bits comprised of input data bits and input check bits, wherein a single one of the IC chips has an insufficient number of available outputs to provide all of the required outputs. The method includes applying the input data bits and the input check bits to the input terminals of each IC chip in an inverse manner relative to one another, and then performing the error detecting and correcting operations on each chip in accordance with an inversely symmetrical Hamming code. In addition, by taking advantage of redundancies in the performance of error detecting operations, the method also provides for automatic self-checking of chip operations.

Abstract: A synchronizing circuit using a switchable bistable element for synchronizing an asymmetric signal with the clock of a data processing system. The occurrence of a balanced or metastable state in the switchable bistable synchronizing element which can slow up the data transfer rate is inhibited by applying an asymmetric injection signal thereto having a frequency, magnitude and asymmetry such that the maintenance of a balanced or metastable state in the synchronizing element is inhibited without interfering with the normal switching operation thereof.