Patents by Inventor Duc Bui
Duc Bui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240137389Abstract: A computer-implemented method is presented for detecting non-compliance with an opt-out decision of a user. The method includes: identifying select statements of a privacy policy for an online tracking entity by analyzing webpages associated with the online tracking entity, where the select statements specify data practices in response to an opt-out decision; detecting transfer of cookies from a web browser to a server, where the cookies are transferred after an opt-out decision by the given user and the server is associated with the given online tracking entity; analyzing content of the detected cookies in relation to the select statements of the privacy policy; and notifying the given user of a violation of the privacy policy in response to determining an inconsistency between the content of the detected cookies and the select statements of the privacy policy.Type: ApplicationFiled: October 12, 2023Publication date: April 25, 2024Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Kang G. SHIN, Hoang Duc BUI
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Patent number: 11960891Abstract: A digital data processor includes an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, an instruction decoder coupled to the instruction memory for sequentially recalling instructions from the instruction memory and determining the data processing operation and the at least one data operand, and at least one operational unit coupled to a data register file and to the instruction decoder to perform a data processing operation upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The at least one operational unit is configured to perform a table write in response to a look up table write instruction by writing at least one data element from a source data register to a specified location in a specified number of at least one table.Type: GrantFiled: March 4, 2022Date of Patent: April 16, 2024Assignee: Texas Instruments IncorporatedInventors: Naveen Bhoria, Duc Bui, Dheera Balasubramanian Samudrala
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Patent number: 11900112Abstract: A method to reverse source data in a processor in response to a vector reverse instruction includes specifying, in respective fields of the vector reverse instruction, a source register containing the source data and a destination register. The source register includes a plurality of lanes and each lane contains a data element, and the destination register includes a plurality of lanes corresponding to the lanes of the source register. The method further includes executing the vector reverse instruction by creating reversed source data by reversing the order of the data elements, and storing the reversed source data in the destination register.Type: GrantFiled: March 28, 2022Date of Patent: February 13, 2024Assignee: Texas Instruments IncorporatedInventors: Timothy D. Anderson, Duc Bui
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Publication number: 20240036867Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction configured to cause the processor to output a first data value to a first address in a first data cache, outputting, by the processor, the first data value to a second address in a second data cache, receiving a second instruction configured to cause a streaming engine associated with the processor to prefetch data from the first data cache, determining that the first data value has not been outputted from the second data cache to the first data cache, stalling execution of the second instruction, receiving an indication, from the second data cache, that the first data value has been output from the second data cache to the first data cache, and resuming execution of the second instruction based on the received indication.Type: ApplicationFiled: October 10, 2023Publication date: February 1, 2024Inventors: Naveen BHORIA, Kai CHIRCA, Timothy D. ANDERSON, Duc BUI, Abhijeet A. CHACHAD, Son Hung TRAN
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Publication number: 20240036866Abstract: Disclosed herein are systems and methods for executing multiple instruction set architectures (ISAs) on a singular processing unit. In an implementation, a processor that includes a first decoder, a second decoder, instruction fetch circuitry, and instruction dispatch circuitry is configured to execute two separate instruction set architectures. In an implementation, the instruction fetch circuitry is configured to fetch instructions from an associated memory. In an implementation the instruction dispatch circuitry is coupled to the instruction fetch circuitry, the first decoder, and the second decoder and is configured to route instructions associated with a first ISA to the first decoder, and route instructions associated with a second ISA to the second decoder.Type: ApplicationFiled: July 20, 2023Publication date: February 1, 2024Inventors: Duc Bui, Timothy D. Anderson, Paul Gauvreau
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Publication number: 20240036876Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.Type: ApplicationFiled: October 16, 2023Publication date: February 1, 2024Inventors: Timothy D. ANDERSON, Duc BUI, Joseph ZBICIAK, Reid E. TATGE
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Publication number: 20240028338Abstract: A digital data processor includes an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, an instruction decoder coupled to the instruction memory for sequentially recalling instructions from the instruction memory and determining the data processing operation and the at least one data operand, and at least one operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to increment histogram values in response to a histogram instruction by incrementing a bin entry at a specified location in a specified number of at least one histogram.Type: ApplicationFiled: October 2, 2023Publication date: January 25, 2024Inventors: Naveen BHORIA, Duc BUI, Rama VENKATASUBRAMANIAN, Dheera Balasubramanian SAMUDRALA, Alan DAVIS
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Publication number: 20240020125Abstract: A digital data processor includes a multi-stage butterfly network, which is configured to, in response to a look up table read instruction, receive look up table data from an intermediate register, reorder the look up table data based on control signals comprising look up table configuration register data, and write the reordered look up table data to a destination register specified by the look up table read instruction.Type: ApplicationFiled: September 29, 2023Publication date: January 18, 2024Inventors: Naveen BHORIA, Duc BUI, Dheera Balasubramanian SAMUDRALA, Rama VENKATASUBRAMANIAN
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Publication number: 20240020121Abstract: A processor includes a functional unit, and a set of vector registers coupled to the functional unit. The processor executes an instruction to cause the functional unit to classify each value of multiple floating-point values stored in a first vector register of the set of vector registers, and store in a second vector register of the set of registers multiple elements that each indicate a respective classification of a respective value of the multiple floating-point values. The first and second vector registers may be source and destination vector registers, and each may be specified by the instruction. The classify and store operations may also be specified by the instruction. The instruction may be embodied on a device-readable medium.Type: ApplicationFiled: September 28, 2023Publication date: January 18, 2024Inventors: Joseph Zbiciak, Brett L. Huber, Duc Bui
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Publication number: 20230367598Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.Type: ApplicationFiled: March 28, 2023Publication date: November 16, 2023Inventors: Duc Bui, Peter Richard Dent, Timothy D. Anderson
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Publication number: 20230359462Abstract: A digital data processor includes an instruction memory storing instructions specifying a data processing operation and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to perform a table write in response to a look up table initialization instruction by duplicating at least one data element from a source data register to create duplicated data elements, and writing the duplicated data elements to a specified location in a specified number of at least one table and a corresponding location in at least one other table.Type: ApplicationFiled: July 17, 2023Publication date: November 9, 2023Inventors: Naveen Bhoria, Dheera Balasubramanian Samudrala, Duc Bui, Rama Venkatasubramanian
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Patent number: 11803382Abstract: A digital data processor includes a multi-stage butterfly network, which is configured to, in response to a look up table read instruction, receive look up table data from an intermediate register, reorder the look up table data based on control signals comprising look up table configuration register data, and write the reordered look up table data to a destination register specified by the look up table read instruction.Type: GrantFiled: September 2, 2022Date of Patent: October 31, 2023Assignee: Texas Instruments IncorporatedInventors: Naveen Bhoria, Duc Bui, Dheera Balasubramanian Samudrala, Rama Venkatasubramanian
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Patent number: 11803379Abstract: A method to classify source data in a processor in response to a vector floating-point classification instruction includes specifying, in respective fields of the vector floating-point classification instruction, a source register containing the source data and a destination register to store classification indications for the source data. The source register includes a plurality of lanes that each contains a floating-point value and the destination register includes a plurality of lanes corresponding to the lanes of the source register. The method further includes executing the vector floating-point classification instruction by, for each lane in the source register, classifying the floating-point value in the lane to identify a type of the floating-point value, and storing a value indicative of the identified type in the corresponding lane of the destination register.Type: GrantFiled: October 11, 2022Date of Patent: October 31, 2023Assignee: Texas Instruments IncorporatedInventors: Joseph Zbiciak, Brett L. Huber, Duc Bui
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Publication number: 20230334309Abstract: Systems, methods, and computer-readable media for generating a synthetic training data set from an original unstructured electronic document are disclosed. The synthetic training data set may be used to train a deep learning model to extract data from the original electronic document. The original electronic document may comprise annotated data fields. Each annotated data field may comprise a bounding box and a label. The original electronic document may comprise a header, a table, and a footer. Macro augmentation operations may be applied to the original electronic document to create sub-templates representative of distinct page layouts in the original electronic document. The synthetic training data set may be generated by applying geometric and semantic data augmentations to the sub-templates and the original electronic documents. The synthetic training data set may then be provided the deep learning model for training.Type: ApplicationFiled: April 14, 2022Publication date: October 19, 2023Inventors: Alexey Streltsov, Monit Shah Singh, Dhananjay Tomar, Christian Reisswig, Minh Duc Bui
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Patent number: 11789742Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.Type: GrantFiled: March 7, 2022Date of Patent: October 17, 2023Assignee: Texas Instruments IncorporatedInventors: Timothy D. Anderson, Duc Bui, Joseph Zbiciak, Reid E. Tatge
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Patent number: 11782718Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction configured to cause the processor to output a first data value to a first address in a first data cache, outputting, by the processor, the first data value to a second address in a second data cache, receiving a second instruction configured to cause a streaming engine associated with the processor to prefetch data from the first data cache, determining that the first data value has not been outputted from the second data cache to the first data cache, stalling execution of the second instruction, receiving an indication, from the second data cache, that the first data value has been output from the second data cache to the first data cache, and resuming execution of the second instruction based on the received indication.Type: GrantFiled: March 30, 2021Date of Patent: October 10, 2023Assignee: Texas Instruments IncorporatedInventors: Naveen Bhoria, Kai Chirca, Timothy D. Anderson, Duc Bui, Abhijeet A. Chachad, Son Hung Tran
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Patent number: 11775302Abstract: A digital data processor includes an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, an instruction decoder coupled to the instruction memory for sequentially recalling instructions from the instruction memory and determining the data processing operation and the at least one data operand, and at least one operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to increment histogram values in response to a histogram instruction by incrementing a bin entry at a specified location in a specified number of at least one histogram.Type: GrantFiled: October 25, 2021Date of Patent: October 3, 2023Assignee: Texas Instruments IncorporatedInventors: Naveen Bhoria, Duc Bui, Rama Venkatasubramanian, Dheera Balasubramanian Samudrala, Alan Davis
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Patent number: 11741751Abstract: Provided is a face recognition method comprising acquiring a masked face image including a masked region and an un-masked region; obtaining an image feature from the masked face image; inputting the image feature to a pre-trained segmentation model to automatically estimate a feature of the masked region; and refining the image feature using the estimated feature of the masked region, wherein the refining step comprising focusing on a feature of the un-masked region and discarding the estimated feature of the masked region.Type: GrantFiled: April 14, 2021Date of Patent: August 29, 2023Assignee: Vinai AI Application and Research Joint Stock Co.Inventors: Hung Hai Bui, Toan Duc Bui, Anh Hoang Pham
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Patent number: 11709677Abstract: A digital data processor includes an instruction memory storing instructions specifying a data processing operation and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to perform a table write in response to a look up table initialization instruction by duplicating at least one data element from a source data register to create duplicated data elements, and writing the duplicated data elements to a specified location in a specified number of at least one table and a corresponding location in at least one other table.Type: GrantFiled: January 18, 2022Date of Patent: July 25, 2023Assignee: Texas Instruments IncorporatedInventors: Naveen Bhoria, Dheera Balasubramanian Samudrala, Duc Bui, Rama Venkatasubramanian
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Publication number: 20230221955Abstract: A method to transpose source data in a processor in response to a vector bit transpose instruction includes specifying, in respective fields of the vector bit transpose instruction, a source register containing the source data and a destination register to store transposed data. The method also includes executing the vector bit transpose instruction by interpreting N×N bits of the source data as a two-dimensional array having N rows and N columns, creating transposed source data by transposing the bits by reversing a row index and a column index for each bit, and storing the transposed source data in the destination register.Type: ApplicationFiled: March 14, 2023Publication date: July 13, 2023Inventors: Joseph Zbiciak, Dheera Balasubramanian Samudrala, Duc Bui