Abstract: A method for providing, based on an emulation schedule, a reset message to multiple circuits is provided. The reset message associates a reset signal with a selected clock cycle for each circuit, in the emulation schedule. The method includes determining a mask for each of the circuits based on the emulation schedule, providing a clock signal to the circuits, the clock signal comprising the selected clock cycle for each circuit, and tuning the reset signal relative to the clock signal based on a center of the selected clock cycle for each circuit. The method also includes providing the reset signal to the circuits and asserting the reset signal in the circuits based on the mask. A system and a non-transitory, machine-readable medium storing instructions to perform the above method are also provided.

Abstract: A method includes programming an FPGA based controller of a master blade with a power scheme. The master blade receives a first power management signal from the master blade and slave blades. The master blade transmits a second power management signal to itself and to the slave blades responsive to the first power management signal. The master blade receives a third power management signal from itself and the slave blades. The power scheme controls an order and delay in which the second power management signal is transmitted to the first master blade and the slave blades. The power scheme controls an order and delay in which the third power management signal is received from the master blade and the slave blades. The system can be expanded by connecting the master blades to a grand master blade and multiple grand master blades to a great grand master blade.