Abstract: Various systems and methods are provided for accessing and traversing one or more complex data structures and generating a functional user interface that can enable non-technical users to quickly and dynamically generate detailed reports (including tables, charts, and/or the like) of complex data including time varying attributes. The user interfaces are interactive such that a user may make selections, provide inputs, and/or manipulate outputs. In response to various user inputs, the system automatically calculates applicable time intervals, accesses and traverses complex data structures (including, for example, a mathematical graph having nodes and edges), calculates complex data based on the traversals and the calculated time intervals, displays the calculated complex data to the user, and/or enters the calculated complex data into the tables, charts, and/or the like. The user interfaces may be automatically updated based on a context selected by the user.

Abstract: Various systems and methods are provided for accessing and traversing one or more complex data structures and generating a functional user interface that can enable non-technical users to quickly and dynamically generate detailed reports (including tables, charts, and/or the like) of complex data including time varying attributes. The user interfaces are interactive such that a user may make selections, provide inputs, and/or manipulate outputs. In response to various user inputs, the system automatically calculates applicable time intervals, accesses and traverses complex data structures (including, for example, a mathematical graph having nodes and edges), calculates complex data based on the traversals and the calculated time intervals, displays the calculated complex data to the user, and/or enters the calculated complex data into the tables, charts, and/or the like. The user interfaces may be automatically updated based on a context selected by the user.

Abstract: This disclosure is directed at least partly to reducing an acceleration of a magnet when a magnet is moved toward an attracting object. An apparatus may include a dampening mechanism to dissipate kinetic energy of the magnet as it traverses within a housing from a first position to a second position. The housing may be at least partially coupled to another surface as a result of a magnetic attraction when the magnet is located in the second position. The dampening mechanism may include use of a fluid and/or gas that is displaced by the magnet to slow acceleration of the magnet as the magnet traverses between the first position and the second position. In some embodiments, the dampening mechanism may be implemented using threads that cause rotation of the magnet or by rollers that slow acceleration of the magnet.

Abstract: A method and circuit thereof for detecting uncorrelated lines of chrominance of a composite video signal. A threshold level for determining whether lines of chrominance are correlated is defined. A comb filter is then used to separate the chrominance information from the luminance information of a composite video signal. In one embodiment, readings for three consecutive scan lines of chrominance are taken. If any of the adjacent scan lines contain the same color information or the difference is less than the threshold level, the scan lines are correlated. Otherwise, the adjacent scan lines are uncorrelated. If the lines are uncorrelated, a band pass filter is used to separate the chrominance component from the composite video signal. If the lines are correlated, the separation performed by the comb filter was appropriate and no other action is necessary.

Abstract: A luminance signal generation circuit with single clamp generates a separate luminance signal Y by combining RGB input signals in a weighted manner within a Y-Matrix circuit. During a burst period the single clamping circuit is enabled. When enabled, the single clamping circuit compares the separate luminance signal Y to a constant reference voltage signal. A difference signal, representing the difference between the separate luminance signal Y and the constant reference voltage signal, is used to adjust a blanking level of the RGB input signals until the blanking level of the separate luminance signal Y is equal to the constant reference voltage signal. During the non-burst periods the single clamping circuit is disabled and the Y-Matrix circuit combines the RGB input signals into the separate luminance signal Y. Preferably, the single clamping circuit sets the blank level of the separate luminance signal Y to a level equal to two volts.

Abstract: A driver circuit with pull down npn transistor drives an output voltage signal in response to an input voltage signal, without high-speed pnp transistors. A first npn transistor provides current to the output node when the output node is at a level equal to and less than the level of the input voltage signal less a base-to-emitter junction drop across the first npn transistor. A second npn transistor sinks current from the output node when the output node is at a level greater than the level of the input voltage signal less the base-to-emitter junction drop across the first npn transistor. The second npn transistor is controlled by a level of a control node. When the level of the output node is greater than the level of the input voltage signal less the base-to-emitter junction drop, the first npn transistor is turned off and the level of the control node is charged up by a current source.

Abstract: A burst gate pulse generator generates a burst gate signal representative of a time period during which a burst signal is present within an input composite video signal. Each period of the input composite video signal includes a horizontal synchronization pulse, a burst signal and a video information signal. The burst gate pulse generator detects the end of the horizontal synchronization signal and begins the burst pulse at the end of the horizontal synchronization signal. A timing circuit including a charge storage device and a charge delivery device controls the duration of the burst pulse. When the burst pulse is activated the charge delivery device begins building a charge across the charge storage device until a threshold value is reached. Once the charge stored across the charge storage device equals the threshold value the burst pulse is deactivated. During the time when the burst pulse is active, the burst signal will be present on the input composite video signal.

Abstract: A burst gate pulse generator circuit generates a burst gate pulse signal representative of a time period during which a burst signal is present within a composite video signal without requiring external components. Each period of the composite video signal includes a horizontal synchronization signal pulse, a burst signal and a video information signal. A pair of integrated capacitors are discharged during the horizontal synchronization pulse. The capacitors are charged at different rates by two current sources after the horizontal synchronization pulse. A first amount of charge across a first capacitor rises above a predetermined threshold level in a first time period. The burst gate pulse signal is activated when the first amount of charge rises above the predetermined threshold level. This occurs before the burst signal is present within the composite video signal. A second amount of charge across a second capacitor rises above the predetermined threshold level in a second time period.

Abstract: A current source and threshold voltage generation circuit generates a current, through a ratio of devices, and a corresponding threshold voltage signal, to be utilized by a timing circuit for generating a timing ramp and determining when the timing ramp crosses the threshold voltage signal. The current is generated through a current generation circuit, using a ratio of matched devices. Preferably, the matched devices are transistors. The current is then utilized by a timing circuit to charge a charge storage device to a level above the level of the threshold voltage signal. The current is also mirrored, appropriately increased and used to generate the threshold voltage signal which is compared to the charge stored on the charge storage device. Accordingly, any errors in the generation of the current are also reflected in the level of the threshold voltage signal, thereby eliminating the potential for errors in the timing ramp signal generated by the timing circuit.

Abstract: A current source and threshold voltage generation circuit generates a current, through a ratio of devices, and a corresponding threshold voltage signal, to be utilized by a timing circuit for generating a timing ramp and determining when the timing ramp crosses the threshold voltage signal. The current is generated through a current generation circuit, using a ratio of matched devices. Preferably, the matched devices are transistors. The current is then utilized by a timing circuit to charge a charge storage device to a level above the level of the threshold voltage signal. The current is also mirrored, appropriately increased and used to generate the threshold voltage signal which is compared to the charge stored on the charge storage device. Accordingly, any errors in the generation of the current are also reflected in the level of the threshold voltage signal, thereby eliminating the potential for errors in the timing ramp signal generated by the timing circuit.

Abstract: A backporch soft-clamp circuit using a servo loop clamps the blank or DC level of a composite video signal to a known value without altering the other components of the signal. The values of the components of the composite video signal are determined by determining their amplitude with respect to the blank level. The backporch soft-clamp circuit sets the blank level to a known value for determining the true value of the components. An output composite video signal is generated which represents the input composite video signal with the blank or pedestal level set to a known DC level. Preferably, the DC level is set to two volts. A burst gate pulse representing the presence of a burst signal within the composite video signal is received by the circuit. During the burst period, the circuit soft clamps the blank level of the output signal to the appropriate level without altering the content of the burst signal. The DC level of the output signal is compared to the appropriate level by a comparator circuit.

Abstract: A horizontal synchronization pulse generation circuit generates a horizontal synchronization pulse to be added to an encoded composite video signal. An input receiving circuit receives an encoded input video signal representing video information received from input video signals. An output video signal represents the encoded input video signal in all portions of the signal except the horizontal synchronization period. During the horizontal synchronization period a current is switched through a path resistor and used to generate the voltage level of the horizontal synchronization pulse. The voltage drop across the path resistor during the horizontal synchronization period is applied directly to the output video signal thereby generating a horizontal synchronization pulse. The current switched through the path resistor is generated by a voltage drop across a current resistor.

Abstract: A method of and apparatus for selectively engaging an internal trap filter and implementing an external trap filter through a single pin routes a separate luminance signal through the pin or through an internal trap filter based on the logical voltage level at the pin. When implementing an external trap filter the external components comprising the filter are coupled between the pin and ground and a voltage level of the pin is maintained at a logical low voltage level. When the pin is at a logical low voltage level, two path switches are closed and the separate luminance signal is routed through the pin to be filtered by the external trap filter. The internal trap filter is engaged by coupling a precision resistor between the pin and a power supply voltage thereby pulling the voltage level of the pin to a logical high voltage level and opening the two path switches to bypass the pin and route the separate luminance signal through an internal trap filter.

Abstract: A video/graphics overlay circuit receives an analog input composite video signal and a digital input composite video signal and combines them into a linear combination output composite video signal depending on the state of one or more mixer control signals. The two composite video input signals are each capacitively coupled to buffer and clamp circuits through which the blank or DC level of each signal is clamped to two volts. The outputs of the buffer and clamp circuits are then fed to a mixer circuit and burst separator circuits. The mixer circuit generates the output composite video signal which is a linear combination of the input composite video signals as controlled by the one or more mixer control signals. The burst separator circuits separate the burst signal from the input composite video signals. The extracted burst signals are then provided to a burst signal phase-locked loop for locking the burst signals of the input composite video signals in phase.

Abstract: A luminance signal generation circuit with single clamp and horizontal synchronization pulse generation circuit generates a separate luminance video signal Y, representing RGB input signals, and having a horizontal synchronization pulse. During a burst period, the single clamping circuit compares the separate luminance signal Y to a reference signal. A difference signal, representing the difference between the separate luminance signal Y and the reference signal, is used to adjust a blanking level of the RGB input signals until the blanking level of the separate luminance signal Y is equal to the reference signal. During the non-burst periods, the single clamping circuit is disabled and a Y-matrix circuit combines the RGB input signals into the separate luminance signal Y. A horizontal synchronization pulse generation circuit generates a horizontal synchronization pulse to be added to the clamped separate luminance signal Y.

Abstract: A burst gate pulse generator generates a burst gate signal representative of a time period during which a burst signal is present within an input composite video signal. Each period of the input composite video signal includes a horizontal synchronization pulse, a burst signal and a video information signal. The burst gate pulse generator detects the end of the horizontal synchronization signal and begins the burst pulse at the end of the horizontal synchronization signal. A timing circuit including a charge storage device and a charge delivery device controls the duration of the burst pulse. When the burst pulse is activated the charge delivery device begins building a charge across the charge storage device until a threshold value is reached. Once the charge stored across the charge storage device equals the threshold value the burst pulse is deactivated. During the time when the burst pulse is active, the burst signal will be present on the input composite video signal.

Abstract: An error regulator circuit for use within a charge pump circuit of a phase-locked loop monitors levels of the control signals used to control the charge pump circuit. When one of the control signals remains at a predetermined voltage level for a predetermined period of time, indicating that the charge pump circuit is in a hold mode or an inactive period of time, the current sources within the charge pump used to charge and discharge a charge pump capacitor are temporarily disabled. During a hold or inactive period when one of the control signals used to control the charge pump circuit remains at the predetermined voltage level for more than a predetermined period of time, the current sources of the charge pump circuit are disabled and the charge pump circuit is prevented from charging or discharging the charge pump capacitor until the current sources are re-enabled, thereby allowing the charge pump circuit to maintain an appropriate level of charge across the capacitor during an inactive or hold period.

Abstract: A video/graphics overlay circuit receives an analog input composite video signal and a digital input composite video signal and combines them into a linear combination output composite video signal depending on the state of one or more mixer control signals. The two composite video input signals are each capacitively coupled to buffer and clamp circuits through which the blank or DC level of each signal is clamped to two volts. The outputs of the buffer and clamp circuits are then fed to a mixer circuit and burst separator circuits. The mixer circuit generates the output composite video signal which is a linear combination of the input composite video signals as controlled by the one or more mixer control signals. The burst separator circuits separate the burst signal from the input composite video signals. The extracted burst signals are then provided to a burst signal phase-locked loop for locking the burst signals of the input composite video signals in phase.

Abstract: A burst separator and slicer circuit separates the burst signal from an input composite video signal. Each period of the input composite video signal includes a horizontal synchronization signal, a burst signal and a video information signal. A burst gate pulse signal representing the presence of the burst signal within the input composite video signal is received by the burst separator and slicer circuit. During the burst period, when the burst gate pulse is active, the burst signal is extracted from the input composite video signal and converted to a square waveform. A differential pair and comparator circuit monitors the input composite video signal and compares it to a constant level reference voltage signal. A constant high voltage level is output when the burst signal is greater than the constant level reference signal. A constant low voltage level is output when the burst signal is less than the constant level reference signal.

Abstract: A chroma lock detector circuit monitors charge pump control signals within a phase-lock loop to determine when two input signals to the phase-lock loop are locked together in phase and generates an output signal which is active when the two input signals are locked together in phase and inactive when the two input signals are not locked together in phase. The charge pump control signals are generated in response to a difference in phase between the two input signals and will become inactive once the two input signals are locked together in phase. When the charge pump control signals are inactive for a predetermined period of time, the output of the chroma lock detector circuit is activated and will remain active until the charge pump control signals are again active. A current source is enabled when either of the control signals are active. The current source builds up a first level of charge on a first capacitor during the burst period.