Abstract: A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor (10) with a metal gate (26). A sacrificial gate layer is patterned to provide a self-aligned source mask. The source regions (20) are thus aligned to the gate (26), and the source diffusion provides a slight overlap (28) for good turn-on characteristics and low leakage. The sacrificial gate layer is capable of withstanding the diffusion temperatures of the DMOS process and is selectively etchable. After the high-temperature processing is completed, the sacrificial gate layer is stripped and a metal gate layer is formed over the substrate, filling the volume left by the stripped sacrificial gate material. In one embodiment, a chemical-mechanical polishing technique is used to planarize the metal gate layer.

Abstract: A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor (10) with a metal gate (26). A sacrificial gate layer is patterned to provide a self-aligned source mask. The source regions (20) are thus aligned to the gate (26), and the source diffusion provides a slight overlap (28) for good turn-on characteristics and low leakage. The sacrificial gate layer is capable of withstanding the diffusion temperatures of the DMOS process and is selectively etchable. After the high-temperature processing is completed, the sacrificial gate layer is stripped and a metal gate layer is formed over the substrate, filling the volume left by the stripped sacrificial gate material. In one embodiment, a chemical-mechanical polishing technique is used to planarize the metal gate layer.

Abstract: A process for forming a trench in a semiconductor material is provided. The process includes (a) providing a semiconductor substrate, a first mask layer adjacent the surface of the semiconductor substrate, and a second mask layer adjacent the surface of the first mask layer, the second mask layer defining a first open area and the first mask layer defining a second open area that is larger than the first open area and aligned therewith in a manner so that in the area of the openings the first mask layer is undercut with respect to the second mask layer; and (b) removing a portion of the semiconductor substrate through the open area defined by the second mask layer to form a trench in said semiconductor substrate. An IC device formed using the process is also provided.