Patents by Inventor Duc Van Huynh

Duc Van Huynh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Intelligent crosstalk delay estimator for integrated circuit design flow
    Patent number: 7043708
    Abstract: A method of estimating crosstalk delay for an integrated circuit design flow includes steps of: (a) receiving an integrated circuit design; (b) selecting a list of blocks for which crosstalk delay is to be estimated from the integrated circuit design; (c) selecting one of a plurality of crosstalk delay estimation algorithms or no crosstalk delay estimation algorithm for each block in the list of blocks; (d) performing the selected one of the plurality of crosstalk delay estimation algorithms or no crosstalk delay estimation algorithm to estimate a delay for each block in the list of blocks; and (e) generating as output the estimated delay for each block in the list of blocks.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: May 9, 2006
    Assignee: LSI Logic Corporation
    Inventors: Alexander Tetelbaum, Duc Van Huynh
  • Intelligent crosstalk delay estimator for integrated circuit design flow
    Publication number: 20040250225
    Abstract: A method of estimating crosstalk delay for an integrated circuit design flow includes steps of: (a) receiving an integrated circuit design; (b) selecting a list of blocks for which crosstalk delay is to be estimated from the integrated circuit design; (c) selecting one of a plurality of crosstalk delay estimation algorithms or no crosstalk delay estimation algorithm for each block in the list of blocks; (d) performing the selected one of the plurality of crosstalk delay estimation algorithms or no crosstalk delay estimation algorithm to estimate a delay for each block in the list of blocks; and (e) generating as output the estimated delay for each block in the list of blocks.
    Type: Application
    Filed: June 9, 2003
    Publication date: December 9, 2004
    Inventors: Alexander Tetelbaum, Duc Van Huynh
  • Integrated circuit design flow with capacitive margin
    Patent number: 6810505
    Abstract: A method of designing an integrated circuit includes receiving as input a representation of a circuit design and a margin factor and scaling a parameter value in the circuit design by the margin factor to account for coupling in the circuit design. The margin factor advantageously reduces the number of iterations in the design flow and avoids the necessity of cross-talk analysis.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: October 26, 2004
    Assignee: LSI Logic Corporation
    Inventors: Alexander Tetelbaum, Maad A. Al-Dabagh, Duc Van Huynh, Ruben Molina, Jr.
  • Integrated circuit design flow with capacitive margin
    Publication number: 20040010761
    Abstract: A method of designing an integrated circuit includes receiving as input a representation of a circuit design and a margin factor and scaling a parameter value in the circuit design by the margin factor to account for coupling in the circuit design. The margin factor advantageously reduces the number of iterations in the design flow and avoids the necessity of cross-talk analysis.
    Type: Application
    Filed: July 10, 2002
    Publication date: January 15, 2004
    Inventors: Alexander Tetelbaum, Maad A. Al-Dabagh, Duc Van Huynh, Ruben Molina