Abstract: A memory system includes a plurality of memory chips, including a first memory chip and a second memory chip, and a controller. The controller includes a first central processing unit (CPU) to process a request received from a host, and a plurality of second CPUs to respectively control operations of the plurality of memory chips through a plurality of channels. An importance table is stored in the controller and includes information about a data programming method for data stored in the memory system, the information about the data programming method corresponding to importance information of the data. The second CPUs are configured to program at least some of the data in both the first memory chip and the second memory chip, based on the importance table, so that at least some of the data is stored in both the first memory chip and the second memory chip as same data.

Abstract: An electronic system includes a host device and a storage device including a first memory device of a volatile type and a second memory device of a nonvolatile type. The first memory device is accessed by the host device through a memory-mapped input-output interface and the second memory device is accessed by the host device through a block accessible interface. The storage device provides a virtual memory region to the host device such that a host-dedicated memory region having a first size included in the first memory device is mapped to the virtual memory region having a second size larger than the first size.

Abstract: An electronic device includes a first communication controller and a second communication controller. The first and second communication controller are configured to communicate wirelessly using respective antennas. The electronic device includes a processor that is configured to execute instructions for determining that the first controller is transmitting a first radio frequency signal, and setting a transmit power of the first controller to a first transmit power value. The processor is configured to execute instructions for determining a duty cycle of the first controller is greater than a packet loss threshold associated with the second controller, and setting the transmit power of the first controller to a second transmit power value. The second transmit power value is less than the first transmit power value.

Abstract: A memory system includes a plurality of memory chips, including a first memory chip and a second memory chip, and a controller. The controller includes a first central processing unit (CPU) to process a request received from a host, and a plurality of second CPUs to respectively control operations of the plurality of memory chips through a plurality of channels. An importance table is stored in the controller and includes information about a data programming method for data stored in the memory system, the information about the data programming method corresponding to importance information of the data. The second CPUs are configured to program at least some of the data in both the first memory chip and the second memory chip, based on the importance table, so that at least some of the data is stored in both the first memory chip and the second memory chip as same data.

Abstract: A memory system includes a plurality of memory chips, including a first memory chip and a second memory chip, and a controller. The controller includes a first central processing unit (CPU) to process a request received from a host, and a plurality of second CPUs to respectively control operations of the plurality of memory chips through a plurality of channels. An importance table is stored in the controller and includes information about a data programming method for data stored in the memory system, the information about the data programming method corresponding to importance information of the data. The second CPUs are configured to program at least some of the data in both the first memory chip and the second memory chip, based on the importance table, so that at least some of the data is stored in both the first memory chip and the second memory chip as same data.

Abstract: A storage device includes a storage region in which first data is stored and that is accessed using a first virtual address, and a memory controller configured to control stored data stored in the storage region. The memory controller predicts second data to be accessed using a second virtual address based on the first virtual address, prefetches the second data into an external device, and modifies a physical address mapped to the second virtual address so that the prefetched second data is accessible by a host in communication with the storage device.

Abstract: A storage device includes a storage region in which first data is stored and that is accessed using a first virtual address, and a memory controller configured to control stored data stored in the storage region. The memory controller predicts second data to be accessed using a second virtual address based on the first virtual address, prefetches the second data into an external device, and modifies a physical address mapped to the second virtual address so that the prefetched second data is accessible by a host in communication with the storage device.

Abstract: An electronic system includes a host device and a storage device including a first memory device of a volatile type and a second memory device of a nonvolatile type. The first memory device is accessed by the host device through a memory-mapped input-output interface and the second memory device is accessed by the host device through a block accessible interface. The storage device provides a virtual memory region to the host device such that a host-dedicated memory region having a first size included in the first memory device is mapped to the virtual memory region having a second size larger than the first size.

Abstract: A memory system includes a plurality of memory chips, including a first memory chip and a second memory chip, and a controller. The controller includes a first central processing unit (CPU) to process a request received from a host, and a plurality of second CPUs to respectively control operations of the plurality of memory chips through a plurality of channels. An importance table is stored in the controller and includes information about a data programming method for data stored in the memory system, the information about the data programming method corresponding to importance information of the data. The second CPUs are configured to program at least some of the data in both the first memory chip and the second memory chip, based on the importance table, so that at least some of the data is stored in both the first memory chip and the second memory chip as same data.

Abstract: A device is described. The device includes a data interface connector, an application processor, and interface circuitry. The application processor can receive signals via an antenna. The interface circuitry can be coupled between the application processor and the data interface connector. The data interface circuitry can determine a change in a signal property of one of the signals, the change being caused by an impedance mismatch between the data interface connector and a media consumption device. The data interface circuitry can also send the application processor a signal property setting corresponding with the change. The application processor can adjust the signal property of a subsequent one of the signals, in response to the signal property setting from the interface circuitry, to obtain an adjusted signal. The application processor can also send the adjusted signal to the media consumption device.

Abstract: A processing device detects an occurrence of the first set of use conditions associated with a power supply line coupled between a power source and a power sink in a user device. The processing device sets a tunable decoupling capacitor on the power supply line to a first capacitance value to reduce a level of electromagnetic interference on the power supply line at a first frequency corresponding to the first capacitance value. When the processing device detects a change from the first set of use conditions associated with the power supply line to a second set of use conditions, the processing device sets the tunable decoupling capacitor to a second capacitance value to reduce a level of electromagnetic interference on the power supply line at a second frequency corresponding to the second capacitance value.

Abstract: Disclosed are a clustering device for a flash memory and a method thereof. The clustering device for a flash memory in accordance with an embodiment of the present invention can gather pages having similar update times and perform a write operation of the pages in a same block. Accordingly, the writing performance of the flash memory can be improved and the lifetime of the flash memory can be increased.