Abstract: An electronic device includes a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address; and a refresh control circuit configured to control a smart refresh operation on the target address.

Abstract: An electronic device includes a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address; and a refresh control circuit configured to control a smart refresh operation on the target address.

Abstract: A memory system includes: a memory controller suitable for: generating a normal refresh command and a target refresh command when a number of inputs of an active command reaches a certain number, and providing the active command, the normal refresh command, the target refresh command, and an address; and a memory device including a plurality of banks and suitable for: performing a target refresh operation on one or more word lines of at least one bank in response to the target refresh command, determining a row hammer risk level per bank by counting, within a periodic interval, a number of inputs of the target refresh command per bank based on the address, and performing a hidden refresh operation corresponding to the row hammer risk level per bank in response to the normal refresh command.

Abstract: An electronic device includes an intelligent refresh control circuit generating an intelligent refresh pulse with a pulse that has a generation period that is adjusted based on the number of generations of an auto refresh signal during an intelligent refresh operation, and an internal refresh signal generation circuit outputting one of a self-refresh pulse including a pulse that is periodically generated by an enable signal during a self-refresh operation and the intelligent refresh pulse as an internal refresh signal.

Abstract: An electronic device includes an intelligent refresh control circuit generating an intelligent refresh pulse with a pulse that has a generation period that is adjusted based on the number of generations of an auto refresh signal during an intelligent refresh operation, and an internal refresh signal generation circuit outputting one of a self-refresh pulse including a pulse that is periodically generated by an enable signal during a self-refresh operation and the intelligent refresh pulse as an internal refresh signal.

Abstract: A memory system includes: a memory controller suitable for: generating a normal refresh command and a target refresh command when a number of inputs of an active command reaches a certain number, and providing the active command, the normal refresh command, the target refresh command, and an address; and a memory device including a plurality of banks and suitable for: performing a target refresh operation on one or more word lines of at least one bank in response to the target refresh command, determining a row hammer risk level per bank by counting, within a periodic interval, a number of inputs of the target refresh command per bank based on the address, and performing a hidden refresh operation corresponding to the row hammer risk level per bank in response to the normal refresh command.

Abstract: Disclosed is a word line control circuit including a first driving unit configured to apply a first power supply voltage or a second power supply voltage to a word line according to a first word line control signal; a second driving unit configured to drop a voltage level of the word line to a first target level during a first period by using a third power supply voltage according to output of the first driving unit and a second word line control signal; and a third driving unit configured to maintain the voltage level of the word line at substantially the first target level during a second period according to a third word line control signal, and to drop the voltage level of the word line to a second target level during a third period by using a fourth power supply voltage.

Abstract: An electronic device includes a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address; and a refresh control circuit configured to control a smart refresh operation on the target address.

Abstract: A memory device may include first and second latch sections configured to respectively store a target address and a recent input address, a comparison unit configured to compare an input address with the target address and the recent input address respectively stored in the first and second latch sections, and output a resultant signal, a counting section configured to increase a count corresponding to the recent address stored in the second latch section in response to the resultant signal, and a control unit configured to check the count of the counting section and update the input address to the second latch section in response to the resultant signal.

Abstract: A semiconductor device may include: a first circuit suitable or generating a limit strobe signal by limiting a toggling period of a strobe signal depending on a change of an input code signal; and a second circuit suitable for synchronizing the input code signal based on the limit strobe signal and outputting a synchronized input code signal as an output code signal.

Abstract: A semiconductor device may include: a first circuit suitable or generating a limit strobe signal by limiting a toggling period of a strobe signal depending on a change of an input code signal; and a second circuit suitable for synchronizing the input code signal based on the limit strobe signal and outputting a synchronized input code signal as an output code signal.

Abstract: A memory device may include first and second latch sections configured to respectively store a target address and a recent input address, a comparison unit configured to compare an input address with the target address and the recent input address respectively stored in the first and second latch sections, and output a resultant signal, a counting section configured to increase a count corresponding to the recent address stored in the second latch section in response to the resultant signal, and a control unit configured to check the count of the counting section and update the input address to the second latch section in response to the resultant signal.

Abstract: A semiconductor device includes a first cell array region disposed adjacent to a second cell array region; a dummy cell region disposed between the first cell array region and the second cell array region, and configured to distinguish the first cell array region from the second cell array region by dummy bit lines; first group segment input/output lines disposed to correspond to the first cell array region when viewed in terms of the dummy bit lines; and second group segment input/output lines disposed to correspond to the second cell array region when viewed in terms of the dummy bit lines.

Abstract: An active control device and a semiconductor device including the same are disclosed, which can control an active command in response to a pin change of a command address. The active control device includes: a bank decoding unit configured to decode a bank address to output a bank selection signal; an active controller configured to output a first active control signal, a second active control signal, and an active delay signal to control an active operation of a bank in response to the bank selection signal, a first active signal, and a second active signal; an address latch unit configured to latch a row address to output an address delay signal; and an address output unit configured to output an address corresponding to the address delay signal.

Abstract: A semiconductor device includes a clock shifter configured to shift an active control signal by a predetermined number of clocks and output a shift signal according to a test signal; a command selection block configured to select any one of the active control signal and the shift signal according to the test signal, and output an active command signal; an active control block configured to control an active state of a bank active signal according to the active command signal; and an address latch block configured to latch an internal address according to the active command signal and the active control signal, and output a row address to a core region.

Abstract: A smart refresh device includes an address control block configured to determine whether a specific row address is a row hammer address, and invert a first row hammer address and perform an addition/subtraction of an address; a repair control block configured to determine whether the row hammer address is a repaired address and output a stored repair address as a second repair control signal; a repair address storage block configured to store an output address of the address control block and output a stored address as a latch address; a fuse block configured to output a repair signal representing information on a repair address to the repair control block, and output a decoding signal according to the latch address; and an operator configured to add and subtract the decoding signal according to an addition signal and a subtraction signal.

Abstract: A semiconductor device includes a clock shifter configured to shift an active control signal by a predetermined number of clocks and output a shift signal according to a test signal; a command selection block configured to select any one of the active control signal and the shift signal according to the test signal, and output an active command signal; an active control block configured to control an active state of a bank active signal according to the active command signal; and an address latch block configured to latch an internal address according to the active command signal and the active control signal, and output a row address to a core region.

Abstract: A smart refresh device includes an address control block configured to determine whether a specific row address is a row hammer address, and invert a first row hammer address and perform an addition/subtraction of an address; a repair control block configured to determine whether the row hammer address is a repaired address and output a stored repair address as a second repair control signal; a repair address storage block configured to store an output address of the address control block and output a stored address as a latch address; a fuse block configured to output a repair signal representing information on a repair address to the repair control block, and output a decoding signal according to the latch address; and an operator configured to add and subtract the decoding signal according to an addition signal and a subtraction signal.

Abstract: A latch circuit includes an input block configured to latch first group input addresses and second group input addresses and output first group internal addresses, according to states of select signals; and a latch block configured to latch the first group internal addresses corresponding to a first active command when a first active control signal is activated, and output the first group internal addresses and second group internal addresses as row addresses corresponding to a second active command when a second active control signal is activated.

Abstract: A semiconductor device includes a first cell array region disposed adjacent to a second cell array region; a dummy cell region disposed between the first cell array region and the second cell array region, and configured to distinguish the first cell array region from the second cell array region by dummy bit lines; first group segment input/output lines disposed to correspond to the first cell array region when viewed in terms of the dummy bit lines; and second group segment input/output lines disposed to correspond to the second cell to array region when viewed in terms of the dummy bit lines.