Patents by Inventor DUDY Avraham
DUDY Avraham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11709621Abstract: A system and method for read threshold calibration in a non-volatile memory are provided. Physical dies in the memory are divided into groups based on device-level parameters such as time and temperature parameters. An outlier die may be identified outside of the plurality of groups based on a comparison of a bit error rate (BER) indicator for each die to a threshold. For each group of dies, a read parameter is determined for at least one die, and applied to each of the plurality of dies of the group. The read parameter may be determined based on a threshold measurement of a representative one or more word lines.Type: GrantFiled: April 14, 2021Date of Patent: July 25, 2023Assignee: Western Digital Technologies Inc.Inventors: Dudy Avraham, Alex Bazarsky, Evgeny Mekhanik
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Publication number: 20220113894Abstract: A system and method for read threshold calibration in a non-volatile memory are provided. Physical dies in the memory are divided into groups based on device-level parameters such as time and temperature parameters. An outlier die may be identified outside of the plurality of groups based on a comparison of a bit error rate (BER) indicator for each die to a threshold. For each group of dies, a read parameter is determined for at least one die, and applied to each of the plurality of dies of the group. The read parameter may be determined based on a threshold measurement of a representative one or more word lines.Type: ApplicationFiled: April 14, 2021Publication date: April 14, 2022Applicant: Western Digital Technologies Inc.Inventors: Dudy Avraham, Alex Bazarsky, Evgeny Mekhanik
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Patent number: 11190219Abstract: An error correcting code (ECC) decoder for a non-volatile memory device is configured to decode data stored by the non-volatile memory device using a parity check matrix with columns of different column weights. The ECC decoder is further configured to artificially slow processing of one or more of the columns of the parity check matrix in response to column weights for the one or more columns satisfying a threshold.Type: GrantFiled: June 30, 2020Date of Patent: November 30, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Ran Zamir, Dudy Avraham, Eran Sharon, Idan Alrod, Idan Goldenberg, Omer Fainzilber, Yuri Ryabinin, Yan Dumchin, Igal Mariasin, Eran Banani
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Patent number: 11061768Abstract: A black box device for a vehicle includes a data storage system for recording event data fed to the black box from various vehicle sensors. The data storage system includes a memory having memory cells and a controller in communication with the memory. The controller is configured to receive data and determine one or more memory cells as a destination for the data to be written. The controller is configured to determine a wear level of the memory cells and select a subset of program states of the memory cells based on the wear level; and program the memory cells using respective subsets of program states for each respective memory cell.Type: GrantFiled: February 14, 2020Date of Patent: July 13, 2021Assignee: Western Digital Technologies, Inc.Inventors: Idan Alrod, Judah Gamliel Hahn, Ariel Navon, Eran Sharon, Dudy Avraham
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Patent number: 10998041Abstract: In a read scan operation, a first read level window is scanned for a first candidate read level that activates the fewest number of memory cells in relation to other candidate read levels within that window. A second read level window for a second candidate read level is then configured based on a correlation between at least one of the two adjacent memory states and one or more other adjacent memory states associated with the second read level window. The second read level window is scanned for a second candidate read level that activates the fewest number of memory cells, or results in the fewest bit errors, in relation to other candidate read levels within the second read level window. Next, a read operation is configured to use the first candidate read level and the second candidate read level.Type: GrantFiled: May 7, 2020Date of Patent: May 4, 2021Assignee: Western Digital Technologies, Inc.Inventors: Dudy Avraham, Alex Bazarsky, Rotem Feinblat, David Rozman
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Patent number: 10892784Abstract: Disclosed herein are memory devices, systems, and methods of encoding and decoding data. In one aspect, an encoded data chunk is received and segmented into data segments with similar features. Each segment can be decoded based on its features. Data can also be rearranged and partitioned so as to minimize an entropy score that is based on the size and entropy of the data partitions. The approach is capable of enhancing performance, reducing decoding latency, and reducing power consumption.Type: GrantFiled: June 3, 2019Date of Patent: January 12, 2021Assignee: Western Digital Technologies, Inc.Inventors: Dudy Avraham, Omer Fainzilber, Tommer Kuper Lotan, Eran Sharon, Ofir Pele, Stella Achtenberg, Ran Zamir
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Patent number: 10879940Abstract: A method for improving decoding and error correction in non-volatile memory, e.g., solid state drives. A map is generated for each data type that has a structure, e.g., text files. The map can be based on the underlying characteristics of this type of the data file and the mutual information between Lout to a soft decoder. The map transforms the data prior to encoding to condition the data to improve decoding and error correction.Type: GrantFiled: May 9, 2019Date of Patent: December 29, 2020Assignee: Western Digital Technologies, Inc.Inventors: Omer Fainzilber, Dudy Avraham
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Publication number: 20200382143Abstract: Disclosed herein are memory devices, systems, and methods of encoding and decoding data. In one aspect, an encoded data chunk is received and segmented into data segments with similar features. Each segment can be decoded based on its features. Data can also be rearranged and partitioned so as to minimize an entropy score that is based on the size and entropy of the data partitions. The approach is capable of enhancing performance, reducing decoding latency, and reducing power consumption.Type: ApplicationFiled: June 3, 2019Publication date: December 3, 2020Applicant: Western Digital Technologies, Inc.Inventors: Dudy Avraham, Omer Fainzilber, Tommer Kuper Lotan, Eran Sharon, Ofir Pele, Stella Achtenberg, Ran Zamir
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Publication number: 20200358458Abstract: A method for improving decoding and error correction in non-volatile memory, e.g., solid state drives. A map is generated for each data type that has a structure, e.g., text files. The map can be based on the underlying characteristics of this type of the data file and the mutual information between Lout to a soft decoder. The map transforms the data prior to encoding to condition the data to improve decoding and error correction.Type: ApplicationFiled: May 9, 2019Publication date: November 12, 2020Applicant: Western Digital Technologies, Inc.Inventors: Omer Fainzilber, Dudy Avraham
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Patent number: 10725781Abstract: Systems and methods for pre-fetching data in a memory device are disclosed. The method includes generating a prior read command data structure and receiving a current read command. The method may include retrieving from the prior read command data structure a predicted next read command based on the received current read command, and pre-fetching data associated with the predicted next read command. The method may further include that after pre-fetching the data associate with the predicted next read command and prior to receiving a next read command, retrieving from the prior read command data structure a second predicted next read command based on the predicted next read command, and pre-fetching data associated with the second predicted next read command.Type: GrantFiled: February 28, 2019Date of Patent: July 28, 2020Assignee: Western Digital Technologies, Inc.Inventors: Dudy Avraham, Ariel Navon, Shay Benisty, Karin Inbar
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Patent number: 10580485Abstract: Disclosed is a system and method for adjusting read levels in a storage device based on bias functions. The method includes receiving a request to perform a memory access operation on a wordline of non-volatile memory. The method also includes selecting a bias function corresponding to the wordline of the non-volatile memory from a group of bias functions. The method also includes determining a bias value based on the selected bias function and the wordline. The method also includes adjusting a read level in the non-volatile memory based on the bias value. The method also includes performing the memory access operation on the wordline of the non-volatile memory using the adjusted read level. The bias functions may be linear functions and adjusted in response to detecting a recalibration condition.Type: GrantFiled: December 20, 2017Date of Patent: March 3, 2020Assignee: Western Digital Technologies, Inc.Inventors: Dudy Avraham, Alexander Bazarsky, Tomer Tzvi Eliash, David Rozman, Eran Sharon, Arthur Shulkin
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Patent number: 10379739Abstract: Embodiments of systems and methods for management and/or optimization of non-volatile memory read thresholds using improved time and temperature tagging are described. In some embodiments, time and temperature tagging can be optimized based on time that it takes to perform read threshold calibration, the expected change in temperature, and/or the impact of this change on bit error rate. In some embodiments, a model of an environmental parameter can be determined and associated read thresholds can be pre-calculated. If the measured environmental parameter is within a threshold of the model for the environmental parameter, a pre-calculated read threshold value can be used instead of performing read threshold calibration. Advantageously, power consumption can be reduced and throughput for the memory device can be increased.Type: GrantFiled: March 23, 2018Date of Patent: August 13, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Alexander Bazarsky, Dudy Avraham, Eran Sharon
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Publication number: 20190189202Abstract: Disclosed is a system and method for adjusting read levels in a storage device based on bias functions. The method includes receiving a request to perform a memory access operation on a wordline of non-volatile memory. The method also includes selecting a bias function corresponding to the wordline of the non-volatile memory from a group of bias functions, The method also includes determining a bias value based on the selected bias function and the wordline.Type: ApplicationFiled: December 20, 2017Publication date: June 20, 2019Inventors: Dudy Avraham, Alexander Bazarsky, Tomer Tzvi Eliash, David Rozman, Eran Sharon, Arthur Shulkin
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Patent number: 10229751Abstract: A storage system is provided comprising a controller and a memory. The controller is configured to identify at least two physical blocks of memory that are designated as bad blocks because of at least one defective wordline; identify which wordlines in the at least two physical blocks of memory are defective; and create a logical block of memory from non-defective wordlines in the at least two physical blocks of memory, wherein some portions of the logical block are mapped to one of the at least two physical blocks of memory, and wherein other portions of the logical block are mapped to another one of the at least two physical blocks of memory.Type: GrantFiled: May 1, 2017Date of Patent: March 12, 2019Assignee: Western Digital Technologies, Inc.Inventors: Dudy Avraham, Ran Zamir, Idan Alrod, Eran Sharon
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Publication number: 20180315487Abstract: A storage system is provided comprising a controller and a memory. The controller is configured to identify at least two physical blocks of memory that are designated as bad blocks because of at least one defective wordline; identify which wordlines in the at least two physical blocks of memory are defective; and create a logical block of memory from non-defective wordlines in the at least two physical blocks of memory, wherein some portions of the logical block are mapped to one of the at least two physical blocks of memory, and wherein other portions of the logical block are mapped to another one of the at least two physical blocks of memory.Type: ApplicationFiled: May 1, 2017Publication date: November 1, 2018Applicant: Western Digital Technologies, Inc.Inventors: DUDY Avraham, Ran Zamir, Idan Alrod, Eran Sharon