Patents by Inventor Dueng-Shiu Tzou

Dueng-Shiu Tzou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8497571
    Abstract: A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a top surface, a bottom surface and a plurality of apertures formed at the bottom surface, wherein the bottom surface of the insulating layer comprises a disposing area and a non-disposing area. Each of the apertures is located at the disposing area and comprises a lateral wall and a base surface. A first thickness is formed between the base surface and the insulating layer, a second thickness is formed between the top surface and the bottom surface, and the second thickness is larger than the first thickness. The chip disposed on the top surface comprises a chip surface and a plurality of bumps. The heat dissipation paste at least fills the apertures and contacts the base surface.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: July 30, 2013
    Assignee: Chipbond Technology Corporation
    Inventors: Chin-Tang Hsieh, Hou-Chang Kuo, Dueng-Shiu Tzou, Chia-Jung Tu, Gwo-Shyan Sheu
  • Patent number: 8471372
    Abstract: A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, wherein the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a first insulating portion and a second insulating portion, the first insulating portion comprises a first upward surface, a first downward surface, a first thickness and a recess formed on the first downward surface, wherein the recess comprises a bottom surface. The second insulating portion comprises a second upward surface, a second downward surface and a second thickness larger than the first thickness. The trace layer is at least formed on the second insulating portion, the chip disposed on top of the substrate is electrically connected with the trace layer and comprises a plurality of bumps, and the heat dissipation paste is disposed at the recess.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: June 25, 2013
    Assignee: Chipbound Technology Corporation
    Inventors: Chin-Tang Hsieh, Hou-Chang Kuo, Dueng-Shiu Tzou, Chia-Jung Tu, Gwo-Shyan Sheu
  • Publication number: 20120080783
    Abstract: A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a top surface, a bottom surface and a plurality of apertures formed at the bottom surface, wherein the bottom surface of the insulating layer comprises a disposing area and a non-disposing area. Each of the apertures is located at the disposing area and comprises a lateral wall and a base surface. A first thickness is formed between the base surface and the insulating layer, a second thickness is formed between the top surface and the bottom surface, and the second thickness is larger than the first thickness. The chip disposed on the top surface comprises a chip surface and a plurality of bumps. The heat dissipation paste at least fills the apertures and contacts the base surface.
    Type: Application
    Filed: June 20, 2011
    Publication date: April 5, 2012
    Inventors: Chin-Tang Hsieh, Rou-Chang Kuo, Dueng-Shiu Tzou, Chia-Jung Tu, Gwo-Shyan Sheu
  • Publication number: 20120074545
    Abstract: A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, wherein the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a first insulating portion and a second insulating portion, the first insulating portion comprises a first upward surface, a first downward surface, a first thickness and a recess formed on the first downward surface, wherein the recess comprises a bottom surface. The second insulating portion comprises a second upward surface, a second downward surface and a second thickness larger than the first thickness. The trace layer is at least formed on the second insulating portion, the chip disposed on top of the substrate is electrically connected with the trace layer and comprises a plurality of bumps, and the heat dissipation paste is disposed at the recess.
    Type: Application
    Filed: June 20, 2011
    Publication date: March 29, 2012
    Inventors: Chin-Tang Hsieh, Hou-Chang Kuo, Dueng-Shiu Tzou, Chia-Jung Tu, Gwo-Shyan Sheu