Abstract: The transistor structure includes a transistor and a plurality of gate lines electrically connected to the transistor, wherein the transistor includes a semiconductor layer and a source and a drain that are disposed on the semiconductor layer, the source is connected to a source region of the semiconductor layer, and the drain is connected to a drain region of the semiconductor layer; and the transistor further includes a plurality of gates disposed corresponding to a channel region of the semiconductor layer, wherein the plurality of gates are spaced in a length direction of the source and the drain, and the plurality of gates are connected to the plurality of gate lines in a one-to-one correspondence. The technical solution of the present application can compensate and adjust the transistor after a working environment temperature changes, to avoid abnormal display.

Abstract: The transistor structure includes a transistor and a plurality of gate lines electrically connected to the transistor, wherein the transistor includes a semiconductor layer and a source and a drain that are disposed on the semiconductor layer, the source is connected to a source region of the semiconductor layer, and the drain is connected to a drain region of the semiconductor layer; and the transistor further includes a plurality of gates disposed corresponding to a channel region of the semiconductor layer, wherein the plurality of gates are spaced in a length direction of the source and the drain, and the plurality of gates are connected to the plurality of gate lines in a one-to-one correspondence. The technical solution of the present application can compensate and adjust the transistor after a working environment temperature changes, to avoid abnormal display.

Abstract: A display panel includes a display area and a non-display area surrounding the display area. The display area includes a plurality of display lines and a plurality of display sub-pixels arranged in arrays. The non-display area further includes a dummy sub-pixel, a driver chip, a feedback line and a compensation line. The driver chip is used for acquiring a current signal of a light-emitting element in the dummy sub-pixel through the feedback line, and generating a compensation signal when the current signal fed back by the feedback line is not equal to the preset threshold value, and also for generating a display compensation signal when the current signal fed back by the feedback line is equal to the preset threshold value, and the display compensation signal is transmitted to the pixel driving circuit of the display sub-pixel through the display line.

Abstract: A display panel includes a display area and a non-display area surrounding the display area. The display area includes a plurality of display lines and a plurality of display sub-pixels arranged in arrays. The non-display area further includes a dummy sub-pixel, a driver chip, a feedback line and a compensation line. The driver chip is used for acquiring a current signal of a light-emitting element in the dummy sub-pixel through the feedback line, and generating a compensation signal when the current signal fed back by the feedback line is not equal to the preset threshold value, and also for generating a display compensation signal when the current signal fed back by the feedback line is equal to the preset threshold value, and the display compensation signal is transmitted to the pixel driving circuit of the display sub-pixel through the display line.

Abstract: The transistor comprises a first insulation layer and at least one switch region; a first function layer and a second function layer are respectively disposed on each side of the first insulation layer in the x direction; a first source is disposed in a source region of the first semiconductor layer, and a first drain is disposed at a drain region of the first semiconductor layer; a second source is disposed in a source region of the second semiconductor layer, and is connected to the first source by a first connection line; a second drain is disposed in a source region of the second semiconductor layer, and is connected to the first drain by a second connection line; the gate structure is insulated from the first semiconductor layer and the second semiconductor layer and is disposed opposite to channel regions of the first semiconductor layer and the second semiconductor layer.