Abstract: A manufacturing method of a semiconductor device includes: forming pillars in a first region of a stack structure in which interlayer insulating layers and sacrificial insulating layers are alternately stacked; forming a slit in a second region of the stack structure; and removing the sacrificial insulating layers in the first region. In the removing of the sacrificial insulating layers in the first region, a portion of each of the sacrificial insulating layers, which is adjacent to the slit, and a portion of each of the sacrificial insulating layers, which is disposed between the pillars, may be removed using different etching materials.

Abstract: A manufacturing method of a semiconductor device includes: forming pillars in a first region of a stack structure in which interlayer insulating layers and sacrificial insulating layers are alternately stacked; forming a slit in a second region of the stack structure; and removing the sacrificial insulating layers in the first region. In the removing of the sacrificial insulating layers in the first region, a portion of each of the sacrificial insulating layers, which is adjacent to the slit, and a portion of each of the sacrificial insulating layers, which is disposed between the pillars, may be removed using different etching materials.

Abstract: The invention is related to a method for manufacturing a semiconductor device having a barrier pattern. The method includes alternately forming first sacrificial layers and insulating layers forming channel patterns penetrating the first sacrificial layers and the insulating layers, and forming a slit penetrating the first sacrificial layers and the insulating layers. In order to form the barrier pattern, the method also includes forming openings by removing the first sacrificial layers through the slit, and respectively forming conductive layers in the openings. The conductive layers include first barrier patterns having inclined inner surfaces and metal patterns in the first barrier patterns.

Abstract: The invention is related to a method for manufacturing a semiconductor device having a barrier pattern. The method includes alternately forming first sacrificial layers and insulating layers forming channel patterns penetrating the first sacrificial layers and the insulating layers, and forming a slit penetrating the first sacrificial layers and the insulating layers. In order to form the barrier pattern, the method also includes forming openings by removing the first sacrificial layers through the slit, and respectively forming conductive layers in the openings. The conductive layers include first barrier patterns having inclined inner surfaces and metal patterns in the first barrier patterns.

Abstract: The invention is related to a method for manufacturing a semiconductor device having a barrier pattern. The method includes alternately forming first sacrificial layers and insulating layers forming channel patterns penetrating the first sacrificial layers and the insulating layers, and forming a slit penetrating the first sacrificial layers and the insulating layers. In order to form the barrier pattern, the method also includes forming openings by removing the first sacrificial layers through the slit, and respectively forming conductive layers in the openings. The conductive layers include first barrier patterns having inclined inner surfaces and metal patterns in the first barrier patterns.

Abstract: The invention is related to a method for manufacturing a semiconductor device having a barrier pattern. The method includes alternately forming first sacrificial layers and insulating layers forming channel patterns penetrating the first sacrificial layers and the insulating layers, and forming a slit penetrating the first sacrificial layers and the insulating layers. In order to form the barrier pattern, the method also includes forming openings by removing the first sacrificial layers through the slit, and respectively forming conductive layers in the openings. The conductive layers include first barrier patterns having inclined inner surfaces and metal patterns in the first barrier patterns.

Abstract: A method of manufacturing a semiconductor memory device comprises forming a plurality of gate lines on a semiconductor substrate, forming an insulating layer on the gate lines, and performing a cleaning process using a surfactant-free cleaning solution having a viscosity of lower than 2 cP and an acidity of lower than 3 pH to remove residue from the surface of the insulating layer.

Abstract: A method of manufacturing a semiconductor device includes forming first and second gate lines over a semiconductor substrate, wherein each second gate line has a greater width than each of the first gate lines, forming a first insulating layer surrounding the top and side walls of the first and the second gate lines so that first air gaps are formed between the first and second gate lines and between the first gate lines, forming a first reaction region in the first insulating layer by diffusing an etchant to a depth less than a target depth from a surface of the first insulating layer, removing the first reaction region, forming second reaction regions in the first insulating layer by diffusing the etchant to the target depth from the surface of the first insulating layer, and removing the second reaction regions exposing a portion of each first and second gate lines.

Abstract: A method of manufacturing a semiconductor memory device comprises forming a plurality of gate lines on a semiconductor substrate, forming an insulating layer on the gate lines, and performing a cleaning process using a surfactant-free cleaning solution having a viscosity of lower than 2 cP and an acidity of lower than 3 pH to remove residue from the surface of the insulating layer.

Abstract: A method of manufacturing a semiconductor device includes forming first and second gate lines over a semiconductor substrate, wherein each second gate line has a greater width than each of the first gate lines, forming a first insulating layer surrounding the top and side walls of the first and the second gate lines so that first air gaps are formed between the first and second gate lines and between the first gate lines, forming a first reaction region in the first insulating layer by diffusing an etchant to a depth less than a target depth from a surface of the first insulating layer, removing the first reaction region, forming second reaction regions in the first insulating layer by diffusing the etchant to the target depth from the surface of the first insulating layer, and removing the second reaction regions exposing a portion of each first and second gate lines.