Abstract: A memory device having memory cells operates in a normal mode, a first self refresh mode, and a second self refresh mode. The first self refresh mode provides a self refresh operation for retaining data stored in the memory cells without an external command. The time required to return to the normal mode from the first self refresh mode is shorter than a reference time. The second self refresh mode also provides the self refresh operation, but a time required to return to the normal mode from the second self refresh mode is longer than the reference time. The normal mode provides a higher operating voltage to the memory cells than does the second self refresh mode.

Abstract: A memory device having memory cells operates in a normal mode, a first self refresh mode, and a second self refresh mode. The first self refresh mode provides a self refresh operation for retaining data stored in the memory cells without an external command. The time required to return to the normal mode from the first self refresh mode is shorter than a reference time. The second self refresh mode also provides the self refresh operation, but a time required to return to the normal mode from the second self refresh mode is longer than the reference time. The normal mode provides a higher operating voltage to the memory cells than does the second self refresh mode.

Abstract: A memory device having memory cells operates in a normal mode, a first self refresh mode, and a second self refresh mode. The first self refresh mode provides a self refresh operation for retaining data stored in the memory cells without an external command. The time required to return to the normal mode from the first self refresh mode is shorter than a reference time. The second self refresh mode also provides the self refresh operation, but a time required to return to the normal mode from the second self refresh mode is longer than the reference time. The normal mode provides a higher operating voltage to the memory cells than does the second self refresh mode.

Abstract: A memory device having memory cells operates in a normal mode, a first self refresh mode, and a second self refresh mode. The first self refresh mode provides a self refresh operation for retaining data stored in the memory cells without an external command. The time required to return to the normal mode from the first self refresh mode is shorter than a reference time. The second self refresh mode also provides the self refresh operation, but a time required to return to the normal mode from the second self refresh mode is longer than the reference time. The normal mode provides a higher operating voltage to the memory cells than does the second self refresh mode.

Abstract: A method of refreshing a semiconductor memory device includes performing a first refresh operation for memory cells included in a memory cell array, and determining whether a command other than a refresh command is applied to the semiconductor memory device in a refresh cycle of the first refresh operation. The method further includes continuing to perform the first refresh operation when a command other the refresh command is applied to the semiconductor memory device in one refresh cycle of the first refresh operation, and performing a second refresh operation when a command other than the refresh command is not applied to the semiconductor memory device in one refresh cycle of the first refresh operation. A refresh time of the second refresh operation is greater than a refresh time of the first refresh operation.

Abstract: A semiconductor memory device including a transistor having a vertical channel structure is provided. The device includes a first sub memory cell array including a first memory cell connected to a first bit lines and including a transistor having a vertical channel structure, a second sub memory cell array including a second memory cell connected to a first inverted bit lines and including a transistor having a vertical channel structure, and a plurality of precharge blocks. In addition, first and second precharge blocks are disposed at first and second sides of the first bit line and precharge the first bit line, and third and fourth precharge blocks are disposed at first and second sides of the first inverted bit line and precharge the first inverted bit line.

Abstract: A redundancy circuit includes at least one fuse set circuit and a fuse control circuit. The at least one fuse set circuit includes a plurality of fuse cells, each of the plurality of fuse cells having a first transistor and a second transistor having same sizes. The first transistor has a first contact resistance and the second transistor has a second contact resistance different from the first contact resistance. Each of the plurality of fuse cells stores a fuse address indicating a defective cell in a repair operation and outputs a repair address corresponding to the stored fuse address. The fuse control circuit, connected to the plurality of fuse cells, controls the plurality of fuse cells in response to a program signal and a precharge signal such that the corresponding fuse address is stored in each of the fuse cells.

Abstract: A semiconductor memory device includes a plurality of memory cell array blocks connected to word lines, source lines, and bit lines, each memory cell array including memory cells each having a transistor with a floating body, a reference voltage generator configured to have a reference memory cell and generate a reference voltage for bit line sensing corresponding to a current flowing into a reference memory cell during a data read operation, first and second prechargers configured to precharge a bit line connected to non-selected memory cells to the reference voltage in response to first and second precharge control signals during the data read operation, and a sense amplifier configured to sense and amplify a voltage difference between a bit line connected to the selected memory cells and a bit line connected to the non-selected memory cells during the data read operation.

Abstract: A semiconductor memory device includes a memory cell array, which includes a cell array having multiple cell blocks. Each cell block includes source and word lines arranged in one direction, bit lines arranged in a perpendicular direction, and memory cells having corresponding floating bodies. Adjacent memory cells share source or drain regions to form common source or drain regions, respectively. The source regions are arranged in a word line direction and connected to corresponding source lines, and the drain regions are arranged in the bit line direction and connected to corresponding bit lines. Gates of the memory cells are arranged in the word line direction and are connected to form the word lines. The source lines are formed on a layer of the word lines, and the bit lines are formed at a different layer to be insulated from the word and source lines.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, where each memory cell includes a transistor with a floating body region in which majority carriers are accumulated in a steady state. In write and read operations, a first data state corresponding to the steady state is written to and read from at least one selected memory cell of the memory cell array by supplying a first bipolar current through the at least one selected memory cell, and a second data state is written to and read from the at least one selected memory cell by supplying a second bipolar current which is smaller than the first bipolar current through the at least one selected memory cell. In a refresh operation, memory cells of the memory cell array storing the second data state are refreshed.

Abstract: A semiconductor memory device including a transistor having a vertical channel structure is provided. The device includes a first sub memory cell array including a first memory cell connected to a first bit lines and including a transistor having a vertical channel structure, a second sub memory cell array including a second memory cell connected to a first inverted bit lines and including a transistor having a vertical channel structure, and a plurality of precharge blocks. In addition, first and second precharge blocks are disposed at first and second sides of the first bit line and precharge the first bit line, and third and fourth precharge blocks are disposed at first and second sides of the first inverted bit line and precharge the first inverted bit line.

Abstract: A redundancy circuit includes at least one fuse set circuit and a fuse control circuit. The at least one fuse set circuit includes a plurality of fuse cells, each of the plurality of fuse cells having a first transistor and a second transistor having same sizes. The first transistor has a first contact resistance and the second transistor has a second contact resistance different from the first contact resistance. Each of the plurality of fuse cells stores a fuse address indicating a defective cell in a repair operation and outputs a repair address corresponding to the stored fuse address. The fuse control circuit, connected to the plurality of fuse cells, controls the plurality of fuse cells in response to a program signal and a precharge signal such that the corresponding fuse address is stored in each of the fuse cells.

Abstract: A semiconductor memory device including a transistor having a vertical channel structure is provided. The device includes a first sub memory cell array including a first memory cell connected to a first bit lines and including a transistor having a vertical channel structure, a second sub memory cell array including a second memory cell connected to a first inverted bit lines and including a transistor having a vertical channel structure, and a plurality of precharge blocks. In addition, first and second precharge blocks are disposed at first and second sides of the first bit line and precharge the first bit line, and third and fourth precharge blocks are disposed at first and second sides of the first inverted bit line and precharge the first inverted bit line.

Abstract: One embodiment includes a plurality of word lines, a plurality of bit lines intersecting with the plurality of word lines, a plurality of memory cells formed at intersections of and connected to the plurality of word lines and the plurality of bit lines. Each of the plurality of memory cells may be a floating body cell. A bit line selecting circuit may be configured to selectively connect each of the plurality of bit lines to an output bit line. The embodiment may further include plurality of sense amplifiers, where the plurality of sense amplifiers is greater than one and less than the plurality of bit lines in number. A sense amplifier switching structure may be configured to selectively connect each of the plurality of sense amplifiers to the output bit line.

Abstract: One embodiment includes a plurality of word lines, a plurality of source lines, a plurality of bit lines intersecting with the plurality of word lines, and a plurality of memory cells formed at intersections of the plurality of word lines and the plurality of bit lines. Each of the plurality of memory cells is a floating body cell. A gate of each floating body cell is connected to one of the word lines, a drain of each floating body cell is connected to one of the bit lines, and a source of each floating body cell is connected to one of the source lines. At least one bit line and source line selecting circuit is configured to selectively connect each of the plurality of bit lines to a first output bit line and to selectively connect the source lines to a source voltage. At least one sense amplifier is configured to sense data based on a voltage on the first output bit line.

Abstract: A semiconductor memory device includes first and second memory cells having floating bodies, each of which includes a gate connected to a word line and an electrode connected to a common source line to store data. A controller applies a first voltage to the common source line, a negative second voltage to the word line, a third voltage as a first sense enable control voltage and the first voltage as a second sense enable control voltage during a first write period of a write operation. The controller also applies a fourth voltage to the common source line and the first voltage to the word line during a second write period of the write operation. The sensing portion amplifies a bit line and an inverted bit line to the third voltage or the first voltage, respectively, during the first write period in response to the first and second sense enable control voltages.

Abstract: A semiconductor memory device includes a plurality of memory cell array blocks connected to word lines, source lines, and bit lines, each memory cell array including memory cells each having a transistor with a floating body, a reference voltage generator configured to have a reference memory cell and generate a reference voltage for bit line sensing corresponding to a current flowing into a reference memory cell during a data read operation, first and second prechargers configured to precharge a bit line connected to non-selected memory cells to the reference voltage in response to first and second precharge control signals during the data read operation, and a sense amplifier configured to sense and amplify a voltage difference between a bit line connected to the selected memory cells and a bit line connected to the non-selected memory cells during the data read operation.

Abstract: A semiconductor device comprising floating body memory cells performs read and write operations by selectively connecting bit lines and inverted bit lines to sense bit lines and inverted sense bit lines.

Abstract: A semiconductor memory device includes a memory cell array, which includes a cell array having multiple cell blocks. Each cell block includes source and word lines arranged in one direction, bit lines arranged in a perpendicular direction, and memory cells having corresponding floating bodies. Adjacent memory cells share source or drain regions to form common source or drain regions, respectively. The source regions are arranged in a word line direction and connected to corresponding source lines, and the drain regions are arranged in the bit line direction and connected to corresponding bit lines. Gates of the memory cells are arranged in the word line direction and are connected to form the word lines. The source lines are formed on a layer of the word lines, and the bit lines are formed at a different layer to be insulated from the word and source lines.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, where each memory cell includes a transistor with a floating body region in which majority carriers are accumulated in a steady state. In write and read operations, a first data state corresponding to the steady state is written to and read from at least one selected memory cell of the memory cell array by supplying a first bipolar current through the at least one selected memory cell, and a second data state is written to and read from the at least one selected memory cell by supplying a second bipolar current which is smaller than the first bipolar current through the at least one selected memory cell.