Abstract: A display device includes: a substrate comprising light-emitting areas and a non-light-emitting area; a light emitting element layer on the substrate; a thin-film encapsulation layer on the light emitting element layer; a wavelength conversion layer on the thin-film encapsulation layer; a binding member on the wavelength conversion layer and comprising an epoxy group; an opposing substrate facing the substrate; a color filter layer on a surface of the opposing substrate; and an auxiliary layer on the color filter layer and comprising an amine group, wherein the binding member and the auxiliary layer are in contact with each other, and the epoxy group of the binding member and the amine group of the auxiliary layer are chemically bonded to each other.

Abstract: A display device includes: a first conductive layer including a signal line, which includes a pad contact part and a line part having a smaller width than the pad contact part along a first direction and extending from the pad contact part in a second direction that intersects the first direction, and a first non-contact pattern, which is spaced apart from the pad contact part, on a first side along the first direction; an insulating layer on the first conductive layer and including a contact hole that partially exposes the first conductive layer; and a second conductive layer on the insulating layer and including a first pad electrode, which is electrically connected to the first conductive layer through the contact hole, wherein the first pad electrode overlaps with the pad contact part and the first non-contact pattern.

Abstract: The present disclosure relates to semiconductor memory devices. An example semiconductor memory device includes a cell region and a peripheral circuit region electrically connected with the cell region. The cell region includes a plurality of gate electrodes spaced apart from each other and stacked in a vertical direction, and a channel structure extending through the plurality of gate electrodes in the vertical direction. The peripheral circuit region includes a substrate, a first element isolation structure, a first gate structure on the first active region, a second element isolation structure, a second gate structure on the second active region, a third element isolation structure, and a third gate structure on the third active region. The third element isolation structure includes a first element isolation pattern and a second element isolation pattern. The first element isolation pattern and the second element isolation pattern include different materials from each other.

Abstract: A semiconductor memory device includes a stacked structure on a substrate and a vertical structure penetrating the stacked structure. The stacked structured includes a plurality of conductive lines stacked on the substrate. The vertical structure may include a vertical insulating pattern and a channel film extending along sidewalls of the vertical insulating pattern. The vertical insulating pattern may include an inner region and an outer region. The outer region of the vertical insulating pattern may be placed between the channel film and the inner region of the vertical insulating pattern, and the outer region of the vertical insulating pattern may include a diffused metal.

Abstract: A semiconductor memory device includes a peripheral circuit structure; and a cell structure including a cell substrate and a gate electrode, on the peripheral circuit structure. The peripheral circuit structure includes a peripheral circuit board including a first surface facing the cell structure and a second surface opposite to the first surface, a first circuit element on the first surface of the peripheral circuit board, a first wiring line electrically connected to the first circuit element in a first interlayer insulating layer, a capacitor dielectric layer covering the second surface of the peripheral circuit board, a first capacitor electrode in the capacitor dielectric layer, a second capacitor electrode spaced apart from the first capacitor electrode in the capacitor dielectric layer, and a first connection via electrically connecting the first capacitor electrode with the first wiring line by passing through the peripheral circuit board.

Abstract: The present disclosure relates to a display device, and more particularly, to a display device capable of preventing a flow of resin for window manufacture, and a method for fabrication thereof. According to an embodiment of the disclosure, a display device comprises a display panel, a polarization plate disposed on the display panel and having a through hole, a hole cover disposed on the polarization plate to cover the through hole of the polarization plate, a light blocking layer disposed on the hole cover and the polarization plate, and a window on the polarization plate, the hole cover, and the light blocking layer. At least a portion of the light blocking layer is disposed between the hole cover and the window.

Abstract: Methods for treating liver cancer in a patient are provided. The methods include steps of administering at least one dose of a therapeutically effective amount of a composition comprising indocyanine green (ICG) and applying a PDT light source to the liver of the patient, wherein the PDT light source comprises a transarterial fiber optic coaxial catheter comprising a laser light, a sheet having an array of light-emitting diode (LED) lights, or a micro-injectable LED implant configured for delivery inside the liver, wherein the PDT light source is applied for a time period sufficient to release reactive oxygen species from the photosensitizing agent and induce apoptosis of cancer cells. A PDT system may include a composition comprising ICG and a PDT device comprising at least one light source enabled for application of light to a target tumor.

Abstract: A method for operating a storage device capable of improving reliability of a memory system is provided. The method includes providing a storage device which includes a first component and a second component; receiving, via a host interface of the storage device, a command for requesting failure possibility information about the storage device from an external device; and providing, via the host interface, the failure possibility information about the storage device to the external device in response to the command.

Abstract: A semiconductor memory device comprises a cell structure and a peripheral circuit structure electrically connected to the cell structure. The peripheral circuit structure comprises an active region, a first gate structure comprising a first gate insulating layer intersecting the active region and in contact with the active region, a second gate structure comprising a second gate insulating layer spaced apart from the first gate structure, and in contact with the active region, and a source/drain region between the first gate structure and the second gate structure. A thickness of the first gate insulating layer is less than a thickness of the second gate insulating layer. The source/drain region comprises a first region adjacent to the first gate structure and a second region adjacent to the second gate structure. A depth of the first region is equal to a depth of the second region.

Abstract: A display device according to an embodiment of the disclosure includes a panel; a camera that does not overlap the panel in a plan view; a polarization layer disposed on the panel; a transmission layer extending to at least a portion of the polarization layer; and a coating layer having a larger area than the panel and disposed over the polarization layer and the transmission layer, wherein the transmission layer overlaps the camera in a plan view.

Abstract: A semiconductor memory device includes a stacked structure on a substrate and a vertical structure penetrating the stacked structure. The stacked structured includes a plurality of conductive lines stacked on the substrate. The vertical structure may include a vertical insulating pattern and a channel film extending along sidewalls of the vertical insulating pattern. The vertical insulating pattern may include an inner region and an outer region. The outer region of the vertical insulating pattern may be placed between the channel film and the inner region of the vertical insulating pattern, and the outer region of the vertical insulating pattern may include a diffused metal.

Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

Abstract: A printed circuit board includes a first insulating layer; a connection via penetrating through at least a portion of the first insulating layer and having an upper surface exposed to an upper surface of the first insulating layer; a cavity penetrating through at least a portion of the first insulating layer and having the upper surface of the first insulating layer as a bottom surface of the cavity; a bridge disposed in the cavity and having a first bridge pad disposed on a lower side of the bridge; and a bonding layer including conductive particles connected to the connection via and the first bridge pad.

Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

Abstract: A semiconductor memory device includes a source layer, a channel structure, gate electrodes on the source layer and spaced apart on a sidewall of the channel structure, and a common source line. The gate electrodes include a first word line group including first and second gate electrodes and a second word line group including third and fourth gate electrodes. The semiconductor memory device, in response to a voltage of the common source line reaching a target voltage, causes an inhibition voltage to be applied to the second word line group and an erase voltage to be applied to the first word line group in a first erase operation interval, and causes the inhibition voltage to be applied to the first word line group and the erase voltage to be applied to the second word line group in a second erase operation interval.

Abstract: The present disclosure relates to a printed circuit board including, a first insulating layer, a first metal layer disposed on the first insulating layer, a bridge disposed on the first metal layer and including a bridge insulating layer and a bridge circuit layer, a second insulating layer disposed on the first insulating layer and covering at least a portion of the bridge, a second metal layer disposed on the second insulating layer, and a connecting via penetrating the bridge and the second insulating layer to connect the first metal layer to the second insulating layer. The connecting via is spaced apart from the bridge circuit layer.

Abstract: A semiconductor memory device includes; a first stacked structure including a first staircase portion, a second stacked structure on the first stacked structure and including a second staircase portion overlapping the first staircase portion, a first contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the first stacked structure and not electrically connected to the second stacked structure, and a second contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the second stacked structure and not electrically connected to the first stacked structure.

Abstract: A storage device, a non-volatile memory device, and a method of operating the non-volatile memory device are provided. The storage device includes a storage controller configured to send a command and program data including a pattern of one or more bits, a non-volatile memory device configured to receive the command and the program data, and a pattern monitoring circuit configured to monitor a pattern of the program data sent from the storage controller. The pattern monitoring circuit is configured to send an abnormal status check bit to the storage controller when the program data includes repeated patterns that are repeated a preset number of times or more, and the storage controller is configured to resend the program data to the non-volatile memory device in response to receiving the abnormal status check bit.

Abstract: A display device includes a substrate including an active area having pixels and a non-active area including a pad region. A pad electrode is disposed in the pad region and includes a first pad electrode and a second pad electrode disposed on the first pad electrode. A first insulating pattern is interposed between the first and second pad electrodes. In a plan view, the first insulating pattern is positioned inside the first pad electrode, and a portion of the second pad electrode overlapping the first insulating pattern protrudes further from the substrate in a thickness direction than a portion of the second pad electrode not overlapping the first insulating pattern. The second pad electrode directly contacts a portion of the upper surface of the first pad electrode. In a plan view, an area of the second pad electrode is greater than an area of the first pad electrode.