Patents by Inventor Duk M. Kim
Duk M. Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11256643Abstract: An information handling system includes first and second devices, a connectivity switch, and a baseboard management controller. The first and second devices are configured to communicate with first and second processors of the information handling system. The connectivity switch is connected between the first and second devices and the first and second processors. The connectivity switch operates in one of a plurality of configurations including a first configuration, a second configuration, and a third configuration. Each of the configurations provides a different connectivity between the first device, the second device, the first processor, and the second processor. The baseboard management controller determines a setup of the first and second devices, and provides a connectivity indication signal to the connectivity switch based on the setup of the first and second devices. The connectivity indication signal identifies one of the configurations for the connectivity switch.Type: GrantFiled: June 21, 2019Date of Patent: February 22, 2022Assignee: Dell Products L.P.Inventors: Isaac Qin Wang, Duk M. Kim
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Patent number: 11243592Abstract: An information handling system includes a controller and first, second and third devices. The devices power-on during a power-on sequence of the information handling system. During the power-on sequence, the controller provides a first power brake signal to the first device via a first power brake line, a second power brake signal to the second device via a second power brake line, and a third power brake signal to the third device via a third power brake line. The controller removes the first power brake signal from the first power brake line. In response to an expiration of a first amount of time, the controller removes the second power brake signal from the second power brake line. In response to an expiration of a second amount of time, the controller removes the third power brake signal from the third power brake line.Type: GrantFiled: August 15, 2019Date of Patent: February 8, 2022Assignee: Dell Products L.P.Inventors: Johan Rahardjo, Jeremiah James Bartlett, Joshua David Anderson, Isaac Qin Wang, Duk M. Kim
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Publication number: 20210048863Abstract: An information handling system includes a controller and first, second and third devices. The devices power-on during a power-on sequence of the information handling system. During the power-on sequence, the controller provides a first power brake signal to the first device via a first power brake line, a second power brake signal to the second device via a second power brake line, and a third power brake signal to the third device via a third power brake line. The controller removes the first power brake signal from the first power brake line. In response to an expiration of a first amount of time, the controller removes the second power brake signal from the second power brake line. In response to an expiration of a second amount of time, the controller removes the third power brake signal from the third power brake line.Type: ApplicationFiled: August 15, 2019Publication date: February 18, 2021Inventors: Johan Rahardjo, Jeremiah James Bartlett, Joshua David Anderson, Isaac Qin Wang, Duk M. Kim
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Publication number: 20200401544Abstract: An information handling system includes first and second devices, a connectivity switch, and a baseboard management controller. The first and second devices are configured to communicate with first and second processors of the information handling system. The connectivity switch is connected between the first and second devices and the first and second processors. The connectivity switch operates in one of a plurality of configurations including a first configuration, a second configuration, and a third configuration. Each of the configurations provides a different connectivity between the first device, the second device, the first processor, and the second processor. The baseboard management controller determines a setup of the first and second devices, and provides a connectivity indication signal to the connectivity switch based on the setup of the first and second devices. The connectivity indication signal identifies one of the configurations for the connectivity switch.Type: ApplicationFiled: June 21, 2019Publication date: December 24, 2020Inventors: Isaac Qin Wang, Duk M. Kim
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Patent number: 10474620Abstract: An information handling system (IHS) and a method of transmitting data in an IHS. The method includes detecting, via a hardware logic device, a first memory transaction request from a first peripheral component interconnect express (PCIe) device to a system memory. The first memory transaction request includes a first system memory address. A second memory transaction request is detected from a second PCIe device to the system memory. The second memory transaction request includes a second system memory address. The method further includes determining if the first system memory address and the second system memory address are the same system memory address. In response to the first and second system memory addresses being the same, the first memory transaction request and the second memory transaction request are coalesced into a common memory transaction request. The common memory transaction request is issued to the system memory.Type: GrantFiled: January 3, 2017Date of Patent: November 12, 2019Assignee: Dell Products, L.P.Inventors: Srikrishna Ramaswamy, Shyamkumar T. Iyer, Duk M. Kim
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Patent number: 10261699Abstract: In accordance with embodiments of the present disclosure, a method of transmitting data in an information handling system may include receiving, at a hardware logic device from a host system processor of the information handling system, an input/output (I/O) command; storing the I/O command in a controller memory of the hardware logic device that emulates to the host system processor a controller memory of a memory storage device; communicating a notification of the I/O command to a plurality of memory storage devices communicatively coupled to the hardware logic device; coalescing a plurality of command fetch requests received from individual memory storage devices of the plurality of memory storage devices into a coalesced command fetch request; communicating the coalesced command fetch request to the controller memory; and duplicating a command fetch response from the controller memory of the coalesced command fetch request to the plurality of memory storage devices.Type: GrantFiled: May 16, 2017Date of Patent: April 16, 2019Assignee: Dell Products L.P.Inventors: Srikrishna Ramaswamy, Shyam T. Iyer, Duk M. Kim
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Patent number: 10235195Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor subsystem having access to a memory subsystem and a device communicatively coupled to the processor subsystem, the device having an endpoint assigned for access by an operating system executing on the processor subsystem such that the endpoint appears to the operating system as a logical hardware adapter, wherein the device is configured to discover a private device coupled to the device, enumerate the private device as a managed device of the device, and map a portion of a virtual address space of an operating system executing on the processor subsystem to the private device, such that the private device is abstracted to the operating system as a virtual memory address of the operating system.Type: GrantFiled: May 30, 2017Date of Patent: March 19, 2019Assignee: Dell Products L.P.Inventors: Shyam T. Iyer, Gaurav Chawla, Duk M. Kim, Srikrishna Ramaswamy
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Publication number: 20180349160Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor subsystem having access to a memory subsystem and a device communicatively coupled to the processor subsystem, the device having an endpoint assigned for access by an operating system executing on the processor subsystem such that the endpoint appears to the operating system as a logical hardware adapter, wherein the device is configured to discover a private device coupled to the device, enumerate the private device as a managed device of the device, and map a portion of a virtual address space of an operating system executing on the processor subsystem to the private device, such that the private device is abstracted to the operating system as a virtual memory address of the operating system.Type: ApplicationFiled: May 30, 2017Publication date: December 6, 2018Applicant: Dell Products L.P.Inventors: Shyam T. IYER, Gaurav CHAWLA, Duk M. KIM, Srikrishna RAMASWAMY
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Publication number: 20180335956Abstract: A method may include, in an information handling system having an accelerator device, a physical storage media device communicatively coupled to the accelerator device, and a processor subsystem having access to the accelerator device which is coupled between the processor subsystem and the physical storage media device, responsive to an input/output command received in an address space of a storage virtual application executing as a virtual machine of a hypervisor executing on the processor subsystem from a host system executing as a second virtual machine of the hypervisor: (i) updating, by the storage virtual application, metadata associated with the input/output command including setting a host system direct memory access address corresponding to a host data buffer of the host system associated with the command; (ii) and ringing, by the storage virtual application, a doorbell for the physical storage media device.Type: ApplicationFiled: May 17, 2017Publication date: November 22, 2018Applicant: Dell Products L.P.Inventors: Shyam T. IYER, Gaurav CHAWLA, Duk M. KIM, Srikrishna RAMASWAMY
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Publication number: 20180335954Abstract: In accordance with embodiments of the present disclosure, a method of transmitting data in an information handling system may include receiving, at a hardware logic device from a host system processor of the information handling system, an input/output (I/O) command; storing the I/O command in a controller memory of the hardware logic device that emulates to the host system processor a controller memory of a memory storage device; communicating a notification of the I/O command to a plurality of memory storage devices communicatively coupled to the hardware logic device; coalescing a plurality of command fetch requests received from individual memory storage devices of the plurality of memory storage devices into a coalesced command fetch request; communicating the coalesced command fetch request to the controller memory; and duplicating a command fetch response from the controller memory of the coalesced command fetch request to the plurality of memory storage devices.Type: ApplicationFiled: May 16, 2017Publication date: November 22, 2018Applicant: Dell Products L.P.Inventors: Srikrishna RAMASWAMY, Shyam T. IYER, Duk M. KIM
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Publication number: 20180336158Abstract: An information handling system may include a processor subsystem, an attached memory, and an accelerator device communicatively coupled to the processor subsystem and interfaced between the processor subsystem and the attached memory, wherein the accelerator device is configured to: interface with a first logical software entity executing on the processor subsystem via a cache-coherent memory interface of the first logical software entity; interface with a second logical software entity executing on the processor subsystem via a non-cache-coherent memory interface of the first logical software entity; and responsive to a request to copy data to a first virtual address space of the first logical software entity from a second virtual address space of the second logical software entity, copy the data from physical address space associated with the second virtual address to the memory such that the first virtual address space maps to the data as stored on the attached memory.Type: ApplicationFiled: May 16, 2017Publication date: November 22, 2018Applicant: Dell Products L.P.Inventors: Shyam T. IYER, Duk M. KIM, Srikrishna RAMASWAMY, Duane John VOTH
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Publication number: 20180189225Abstract: An information handling system (IHS) and a method of transmitting data in an IHS. The method includes detecting, via a hardware logic device, a first memory transaction request from a first peripheral component interconnect express (PCIe) device to a system memory. The first memory transaction request includes a first system memory address. A second memory transaction request is detected from a second PCIe device to the system memory. The second memory transaction request includes a second system memory address. The method further includes determining if the first system memory address and the second system memory address are the same system memory address. In response to the first and second system memory addresses being the same, the first memory transaction request and the second memory transaction request are coalesced into a common memory transaction request. The common memory transaction request is issued to the system memory.Type: ApplicationFiled: January 3, 2017Publication date: July 5, 2018Inventors: SRIKRISHNA RAMASWAMY, SHYAMKUMAR T. IYER, DUK M. KIM
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Patent number: 9262197Abstract: Methods and systems for I/O acceleration using an I/O accelerator device on a virtualized information handling system include pre-boot configuration of first and second device endpoints that appear as independent devices. After loading a storage virtual appliance that has exclusive access to the second device endpoint, a hypervisor may detect and load drivers for the first device endpoint. The storage virtual appliance may then initiate data transfer I/O operations using the I/O accelerator device. The data transfer operations may be read or write operations to a storage device that the storage virtual appliance provides access to. The I/O accelerator device may use direct memory access (DMA).Type: GrantFiled: July 16, 2014Date of Patent: February 16, 2016Assignee: Dell Products L.P.Inventors: Gaurav Chawla, Robert Wayne Hormuth, Shyamkumar T. Iyer, Duk M. Kim
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Publication number: 20160019079Abstract: Methods and systems for I/O acceleration using an I/O accelerator device on a virtualized information handling system include pre-boot configuration of first and second device endpoints that appear as independent devices. After loading a storage virtual appliance that has exclusive access to the second device endpoint, a hypervisor may detect and load drivers for the first device endpoint. The storage virtual appliance may then initiate data transfer I/O operations using the I/O accelerator device. The data transfer operations may be read or write operations to a storage device that the storage virtual appliance provides access to. The I/O accelerator device may use direct memory access (DMA).Type: ApplicationFiled: July 16, 2014Publication date: January 21, 2016Inventors: Gaurav CHAWLA, Robert Wayne HORMUTH, Shyamkumar T. IYER, Duk M. KIM
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Patent number: 6375071Abstract: A mailbox includes a housing for receiving and storing mail, the housing having a first upper opening through which mail can be deposited and retrieved, and a second lower opening through which mail can be retrieved; a mailbox door mounted to the housing for movement between a first door position in covering relation to the first opening and a second door position out of the covering relation; and a lockable door movable between a first locked position in covering relation to the second opening and a second unlocked position out of the covering relation to permit access to the housing. A mail support is movably mounted within the housing for movement between a first mail support position for supporting mail adjacent the first opening and a second position for supplying mail to a lower portion of the housing adjacent the second opening.Type: GrantFiled: April 10, 2000Date of Patent: April 23, 2002Inventor: Duk M. Kim
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Patent number: 6269626Abstract: A combined cycle cogeneration power plant includes a combustion turbine formed by an inlet for receiving fuel, an inlet for receiving air, a combustor for burning the combustion fuel and the air, and an outlet through which hot gaseous combustion product is released; a regenerative fuel heating system formed by a plurality of heat exchangers for transferring heat to combustion fuel for heating the combustion fuel, and modulating control valves for controlling temperature of the combustion fuel; a heat recovery steam generator (HRSG) connected to the outlet of the combustion turbine for receiving the gaseous combustion product. The HRSG is formed by a plurality of heat exchangers including steam/water drums, each having a surface blowdown connection, and evaporators connected to the steam/water drums, a water inlet connected with the heat exchangers of the HRSG, a steam outlet, and a stack for releasing the exhausted gaseous combustion product.Type: GrantFiled: March 31, 2000Date of Patent: August 7, 2001Inventor: Duk M. Kim
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Patent number: 5938113Abstract: A mailbox includes a housing for receiving and storing mail, the housing having a first upper opening through which mail can be deposited and retrieved, and a second lower opening through which mail can be retrieved; a mailbox door mounted to the housing for movement between a first door position in covering relation to the first opening and a second door position out of the covering relation; and a lockable door movable between a first locked position in covering relation to the second opening and a second unlocked position out of the covering relation to permit access to the housing. A mail support is movably mounted within the housing for movement between a first mail support position for supporting mail adjacent the first opening and a second position for supplying mail to a lower portion of the housing adjacent the second opening.Type: GrantFiled: April 8, 1998Date of Patent: August 17, 1999Inventor: Duk M. Kim