Patents by Inventor Duk Su Chun
Duk Su Chun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11302633Abstract: A fuse latch of a semiconductor device is disclosed. The fuse latch of the semiconductor device includes a plurality of PMOS transistors and a plurality of NMOS transistors. The fuse latch includes PMOS transistors and NMOS transistors configured to latch fuse cell data. In the fuse latch, the plurality of PMOS transistors and the plurality of NMOS transistors are arranged in a shape of two lines in each active region in a second direction.Type: GrantFiled: July 14, 2020Date of Patent: April 12, 2022Assignee: SK hynix Inc.Inventor: Duk Su Chun
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Publication number: 20210202381Abstract: A fuse latch of a semiconductor device is disclosed. The fuse latch of the semiconductor device includes a plurality of PMOS transistors and a plurality of NMOS transistors. The fuse latch includes PMOS transistors and NMOS transistors configured to latch fuse cell data. In the fuse latch, the plurality of PMOS transistors and the plurality of NMOS transistors are arranged in a shape of two lines in each active region in a second direction.Type: ApplicationFiled: July 14, 2020Publication date: July 1, 2021Applicant: SK hynix Inc.Inventor: Duk Su CHUN
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Publication number: 20200090774Abstract: A fuse latch of a semiconductor device is disclosed. The fuse latch includes a plurality of PMOS transistors and a plurality of NMOS transistors to latch fuse cell data. In the fuse latch, the PMOS transistors are formed in a single P-type active region, and the NMOS transistors are arranged in a two-stage structure at one side of the P-type active region.Type: ApplicationFiled: December 10, 2018Publication date: March 19, 2020Applicant: SK hynix Inc.Inventor: Duk Su CHUN
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Patent number: 10573398Abstract: A fuse latch of a semiconductor device is disclosed. The fuse latch includes a plurality of PMOS transistors and a plurality of NMOS transistors to latch fuse cell data. In the fuse latch, the PMOS transistors are formed in a single P-type active region, and the NMOS transistors are arranged in a two-stage structure at one side of the P-type active region.Type: GrantFiled: December 10, 2018Date of Patent: February 25, 2020Assignee: SK hynix Inc.Inventor: Duk Su Chun
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Patent number: 10565055Abstract: A semiconductor memory device may be disclosed. The semiconductor memory device may include a first memory cell array region and a second memory cell array region, each of which includes memory cells. The semiconductor memory device may include a column driving (Y-HOLE) region disposed between the first memory cell array region and the second memory cell array region. The Y-HOLE region may include an error correction code (ECC) block configured for performing error correction.Type: GrantFiled: August 18, 2017Date of Patent: February 18, 2020Assignee: SK hynix Inc.Inventor: Duk Su Chun
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Publication number: 20180181463Abstract: A semiconductor memory device may be disclosed. The semiconductor memory device may include a first memory cell array region and a second memory cell array region, each of which includes memory cells. The semiconductor memory device may include a column driving (Y-HOLE) region disposed between the first memory cell array region and the second memory cell array region. The Y-HOLE region may include an error correction code (ECC) block configured for performing error correction.Type: ApplicationFiled: August 18, 2017Publication date: June 28, 2018Applicant: SK hynix Inc.Inventor: Duk Su CHUN
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Publication number: 20180182722Abstract: A semiconductor memory device having dummy word lines is disclosed. In the semiconductor memory device, a number of dummy word lines are arranged at both ends of a cell mat.Type: ApplicationFiled: August 18, 2017Publication date: June 28, 2018Applicant: SK hynix Inc.Inventors: Young Min KIM, Sung Ho KIM, Sung Soo CHI, Duk Su CHUN
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Patent number: 9997223Abstract: A semiconductor device may be provided. The semiconductor device may include a first power line located in a memory cell array region. The semiconductor device may include a second power line located in a column decoder region. The semiconductor device may include a third power line formed in a layer different from the first power line and the second power line, configured to couple the first power line to the second power line. The semiconductor device may include a metal-oxide-semiconductor (MOS) capacitor located below the third power line.Type: GrantFiled: April 12, 2017Date of Patent: June 12, 2018Assignee: SK hynix Inc.Inventor: Duk Su Chun
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Publication number: 20180025762Abstract: A semiconductor device may be provided. The semiconductor device may include a first power line located in a memory cell array region. The semiconductor device may include a second power line located in a column decoder region. The semiconductor device may include a third power line formed in a layer different from the first power line and the second power line, configured to couple the first power line to the second power line. The semiconductor device may include a metal-oxide-semiconductor (MOS) capacitor located below the third power line.Type: ApplicationFiled: April 12, 2017Publication date: January 25, 2018Applicant: SK hynix Inc.Inventor: Duk Su CHUN
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Patent number: 9842837Abstract: Disclosed is a semiconductor device including a plurality of conductive patterns formed on a semiconductor substrate while being spaced apart from one another at a preset interval and extending in a first direction, and a plurality of junction areas formed by doping impurities in the semiconductor substrate and provided between the conductive patterns. The plurality of junction areas includes transistor junction areas and dummy junction areas. Each of the transistor junction areas is connected through a contact to a source/drain electrode, and the contact is formed at a higher level than the transistor junction areas. Each of the dummy junction areas is connected to a bias contact formed at higher level than the dummy junction areas. A well bias voltage is applied to the dummy junction areas through the bias contact.Type: GrantFiled: February 10, 2016Date of Patent: December 12, 2017Assignee: SK Hynix Inc.Inventor: Duk Su Chun
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Patent number: 9842632Abstract: A bit line equalizer includes a first line-shaped gate extended in a first direction, a second line-shaped gate spaced apart from the first line-shaped gate by a predetermined distance and extending parallel to the first gate, a third gate configured to interconnect the first gate and the second gate, a first contact node located at one side of the first gate, a second contact node located at one side of the second gate, a third contact node located between the first gate and the second gate and located at one side of the third gate, and a fourth contact node located between the first gate and the second gate and located at the other side of the third gate.Type: GrantFiled: February 18, 2016Date of Patent: December 12, 2017Assignee: SK hynix Inc.Inventor: Duk Su Chun
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Publication number: 20170162231Abstract: A memory device may be provided. The memory device may include a plurality of channel areas including a plurality of cell array areas. The memory device may include power interconnections and capacitor areas extended between the plurality of cell array areas in the plurality of channel areas.Type: ApplicationFiled: June 20, 2016Publication date: June 8, 2017Inventor: Duk Su CHUN
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Publication number: 20170084319Abstract: A bit line equalizer includes a first line-shaped gate extended in a first direction, a second line-shaped gate spaced apart from the first line-shaped gate by a predetermined distance and extending parallel to the first gate, a third gate configured to interconnect the first gate and the second gate, a first contact node located at one side of the first gate, a second contact node located at one side of the second gate, a third contact node located between the first gate and the second gate and located at one side of the third gate, and a fourth contact node located between the first gate and the second gate and located at the other side of the third gate.Type: ApplicationFiled: February 18, 2016Publication date: March 23, 2017Inventor: Duk Su CHUN
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Publication number: 20170062417Abstract: Disclosed is a semiconductor device including a plurality of conductive patterns formed on a semiconductor substrate while being spaced apart from one another at a preset interval and extending in a first direction, and a plurality of junction areas formed by doping impurities in the semiconductor substrate and provided between the conductive patterns. The plurality of junction areas includes transistor junction areas and dummy junction areas. Each of the transistor junction areas is connected through a contact to a source/drain electrode, and the contact is formed at a higher level than the transistor junction areas. Each of the dummy junction areas is connected to a bias contact formed at higher level than the dummy junction areas. A well bias voltage is applied to the dummy junction areas through the bias contact.Type: ApplicationFiled: February 10, 2016Publication date: March 2, 2017Inventor: Duk Su CHUN
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Patent number: 9111594Abstract: A semiconductor integrated circuit device includes a first signal line and a second signal line, and a sense amplifier that includes a plurality of PMOS transistors and a plurality of NMOS transistors. The sense amplifier is configured to sense amplify a potential difference between the first signal line and the second signal line. The junction regions of the NMOS and PMOS transistors having the same conductivity type, and to which the same signal is applied, are formed in one integrated active region.Type: GrantFiled: September 23, 2014Date of Patent: August 18, 2015Assignee: SK Hynix Inc.Inventor: Duk Su Chun
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Publication number: 20150041902Abstract: A semiconductor apparatus includes a first junction region formed over an active region; a gate region formed over the active region to substantially surround the first junction region; a second junction region formed over the active region outside the gate region on a first side of the first junction region; and a third junction region formed over the active region outside the gate region on a second side of the first junction region which is opposite to the first side, wherein the second junction region and the third junction region are disposed such that the gate region exists between the second junction region and the third junction region.Type: ApplicationFiled: December 9, 2013Publication date: February 12, 2015Applicant: SK hynix Inc.Inventor: Duk Su CHUN
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Publication number: 20150009771Abstract: A semiconductor integrated circuit device includes a first signal line and a second signal line, and a sense amplifier that includes a plurality of PMOS transistors and a plurality of NMOS transistors. The sense amplifier is configured to sense amplify a potential difference between the first signal line and the second signal line. The junction regions of the NMOS and PMOS transistors having the same conductivity type, and to which the same signal is applied, are formed in one integrated active region.Type: ApplicationFiled: September 23, 2014Publication date: January 8, 2015Inventor: Duk Su CHUN
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Patent number: 8872277Abstract: A semiconductor integrated circuit device includes a first signal line and a second signal line, and a sense amplifier that includes a plurality of PMOS transistors and a plurality of NMOS transistors. The sense amplifier is configured to sense amplify a potential difference between the first signal line and the second signal line. The junction regions of the NMOS and PMOS transistors having the same conductivity type, and to which the same signal is applied, are formed in one integrated active region.Type: GrantFiled: July 13, 2011Date of Patent: October 28, 2014Assignee: SK Hynix Inc.Inventor: Duk Su Chun
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Patent number: 8406079Abstract: Various embodiments of a control circuit for controlling an address output timing of a semiconductor device are disclosed. In one exemplary embodiment, the circuit may include: a timing signal generation unit configured to decode operation specification information of a semiconductor device and generate a timing signal by delaying a read command or a write command based on a decoding result of the operation specification information; a storage control signal generation unit configured to generate a storage control signal in response to the read command or the write command; an output control signal generation unit configured to generate an output control signal in response to the timing signal; and a storage/output unit configured to store an address in response to the storage control signal, and output the stored address as a timing-adjusted address in response to the output control signal.Type: GrantFiled: December 16, 2010Date of Patent: March 26, 2013Assignee: SK Hynix Inc.Inventors: Young Park Kim, Duk Su Chun
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Publication number: 20120154046Abstract: A semiconductor integrated circuit device includes a first signal line and a second signal line, and a sense amplifier that includes a plurality of PMOS transistors and a plurality of NMOS transistors. The sense amplifier is configured to sense amplify a potential difference between the first signal line and the second signal line. The junction regions of the NMOS and PMOS transistors having the same conductivity type, and to which the same signal is applied, are formed in one integrated active region.Type: ApplicationFiled: July 13, 2011Publication date: June 21, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Duk Su CHUN