Abstract: A method of fabricating a vertically tapered structure. The method includes placing a spacer layer at a predetermined area on a wafer, placing a mask layer at a predetermined area on the spacer layer, and over-etching the spacer layer, by etching a certain area below the mask layer, fabricating a cantilever type shadow mask having the spacer layer and the mask layer. Thus, it is possible to fabricate the vertically tapered structure of several tens of microns. The vertically tapered structure can be used as the optical waveguide in the optical device to minimize junction loss that may occur between the optical waveguide and the optical fiber.

Abstract: A method of fabricating a vertically tapered structure. The method includes placing a spacer layer at a predetermined area on a wafer, placing a mask layer at a predetermined area on the spacer layer, and over-etching the spacer layer, by etching a certain area below the mask layer, fabricating a cantilever type shadow mask having the spacer layer and the mask layer. Thus, it is possible to fabricate the vertically tapered structure of several tens of microns. The vertically tapered structure can be used as the optical waveguide in the optical device to minimize junction loss that may occur between the optical waveguide and the optical fiber.

Abstract: A method of fabricating a vertically tapered structure. The method includes placing a spacer layer at a predetermined area on a wafer, placing a mask layer at a predetermined area on the spacer layer, and over-etching the spacer layer, by etching a certain area below the mask layer, fabricating a cantilever type shadow mask having the spacer layer and the mask layer. Thus, it is possible to fabricate the vertically tapered structure of several tens of microns. The vertically tapered structure can be used as the optical waveguide in the optical device to minimize junction loss that may occur between the optical waveguide and the optical fiber.

Abstract: Disclosed is a method for fabricating planar light waveguide circuits, wherein the circuit has a structure that includes a substrate comprised of a core and under-clad layers, an optical circuit, and a plurality of arrayed waveguides coupled thereon. More specifically, the method includes the steps of layering a hard layer on the core layer for forming a mask pattern of the planar light waveguide circuit; forming the mask pattern on the hard layer; layering a photoresist layer on a branch of the optical circuit and the arrayed waveguides of the mask pattern; forming a vertical taper structure on the photoresist layer using a gray scale mask; and, etching the core layer using the photoresist layer with the vertical taper structure and the mask pattern.

Abstract: Disclosed are a flip-chip bonding structure for improving the vertical alignment of an optical device relative to a PLC and a flip-chip bonding method for achieving this structure. The flip-chip bonding structure includes: a semiconductor substrate; a lower-clad layer formed on the upper surface of the semiconductor substrate, wherein the lower-clad layer is depressed on a designated area for mounting an optical device; vertical alignment structures formed on a part of the upper surface of the depressed area of the lower-clad layer and determining a vertical alignment position of the optical device on the semiconductor substrate; electrodes formed on another part of the upper surface of the depressed area of the lower-clad layer; a solder bump formed on the upper surfaces of the electrodes; and, an optical device bonded to the substrate by a flip-chip bonding method using the solder bump.

Abstract: Disclosed are a flip-chip bonding structure for improving the vertical alignment of an optical device relative to a PLC and a flip-chip bonding method for achieving this structure. The flip-chip bonding structure includes: a semiconductor substrate; a lower-clad layer formed on the upper surface of the semiconductor substrate, wherein the lower-clad layer is depressed on a designated area for mounting an optical device; vertical alignment structures formed on a part of the upper surface of the depressed area of the lower-clad layer and determining a vertical alignment position of the optical device on the semiconductor substrate; electrodes formed on another part of the upper surface of the depressed area of the lower-clad layer; a solder bump formed on the upper surfaces of the electrodes; and, an optical device bonded to the substrate by a flip-chip bonding method using the solder bump.

Abstract: A wavelength-division-multiplexing system is disclosed and includes: a semiconductor-amplification section for amplifying each inputted channel with amplification factors corresponding to the compensation signals received therein; a multiplexer for multiplexing a plurality of channels inputted from the semiconductor-amplification section and outputting the multiplexed signals; an optical-detection section for splitting a part of the multiplexed optical signals inputted from the multiplexer, demultiplexing the split optical signals into a plurality of channels, converting each of the demultiplexed channels into corresponding electric signals, and outputting the electric signals; and, a control section calculating the pertinent intensity deviations by comparing each intensity of the electric signals inputted from the optical-detection section with a preset reference intensity and outputting compensation signals for compensating the intensity deviation of each channel to the semiconductor-amplification section.

Abstract: Disclosed is a method for manufacturing a tapered optical waveguide through which waveguides of different sizes are connected with each other optically. In the method, a photo-resist pattern having an inclined profile is formed on the core layer by means of a gray-scale mask, then the profile of the tapered waveguide can be precisely controlled by controlling the profile of the photo-resist pattern and the etching-selection ratio between the photo-resist and the core layer.

Abstract: Disclosed is a method for fabricating planar light waveguide circuits, wherein the circuit has a structure that includes a substrate comprised of a core and under-clad layers, an optical circuit, and a plurality of arrayed waveguides coupled thereon. More specifically, the method includes the steps of layering a hard layer on the core layer for forming a mask pattern of the planar light waveguide circuit; forming the mask pattern on the hard layer; layering a photoresist layer on a branch of the optical circuit and the arrayed waveguides of the mask pattern; forming a vertical taper structure on the photoresist layer using a gray scale mask; and, etching the core layer using the photoresist layer with the vertical taper structure and the mask pattern.

Abstract: Disclosed are a flip-chip bonding structure for improving the vertical alignment of an optical device relative to a PLC and a flip-chip bonding method for achieving this structure. The flip-chip bonding structure includes: a semiconductor substrate; a lower-clad layer formed on the upper surface of the semiconductor substrate, wherein the lower-clad layer is depressed on a designated area for mounting an optical device; vertical alignment structures formed on a part of the upper surface of the depressed area of the lower-clad layer and determining a vertical alignment position of the optical device on the semiconductor substrate; electrodes formed on another part of the upper surface of the depressed area of the lower-clad layer; a solder bump formed on the upper surfaces of the electrodes; and, an optical device bonded to the substrate by a flip-chip bonding method using the solder bump.

Abstract: Disclosed is a method for manufacturing a tapered optical waveguide through which waveguides of different sizes are connected with each other optically. In the method, a photo-resist pattern having an inclined profile is formed on the core layer by means of a gray-scale mask, then the profile of the tapered waveguide can be precisely controlled by controlling the profile of the photo-resist pattern and the etching-selection ratio between the photo-resist and the core layer.

Abstract: Disclosed are a flip-chip bonding structure for improving the vertical alignment of an optical device relative to a PLC and a flip-chip bonding method for achieving this structure. The flip-chip bonding structure includes: a semiconductor substrate; a lower-clad layer formed on the upper surface of the semiconductor substrate, wherein the lower-clad layer is depressed on a designated area for mounting an optical device; vertical alignment structures formed on a part of the upper surface of the depressed area of the lower-clad layer and determining a vertical alignment position of the optical device on the semiconductor substrate; electrodes formed on another part of the upper surface of the depressed area of the lower-clad layer; a solder bump formed on the upper surfaces of the electrodes; and, an optical device bonded to the substrate by a flip-chip bonding method using the solder bump.

Abstract: There is provided a metal etching mask fabrication method. Chrome is first sputtered on a silica layer and a photoresist, which is thicker than the chrome layer, is deposited on the chrome layer. The photoresist layer is patterned, a first nickel is sputtered on the photoresist pattern layer and onto a first portion of the chrome layer exposed by the patterning. A second nickel layer is formed on the portions of the first nickel layer in contact with the first portion of the chrome layer by electroplating. The photoresist pattern has side walls having acute angles to prevent contact between the first nickel layer on the photoresist and the second nickel layer on the first portion of the chrome layer. The photoresist pattern layer and the first nickel layer formed on the photoresist pattern layer are removed using a solvent, and the chrome layer is removed by dry etching in plasma using a gas.

Abstract: There is provided a metal etching mask fabrication method. Chrome is first sputtered on a silica layer and a photoresist, which is thicker than the chrome layer, is deposited on the chrome layer. The photoresist layer is patterned, a first nickel is sputtered on the photoresist pattern layer and onto a first portion of the chrome layer exposed by the patterning. A second nickel layer is formed on the portions of the first nickel layer in contact with the first portion of the chrome layer by electroplating. The photoresist pattern has side walls having acute angles to prevent contact between the first nickel layer on the photoresist and the second nickel layer on the first portion of the chrome layer. The photoresist pattern layer and the first nickel layer formed on the photoresist pattern layer are removed using a solvent, and the chrome layer is removed by dry etching in plasma using a gas.

Abstract: A polyester filamentary yarn having a novel internal microstructure, a polyester tire cord produced from the yarn and a process for production thereof are provided. The polyester yarn of the present invention comprising at least 90 mol % polyethylene terephthalate and having a fineness of 3 to 5 denier per filament, wherein said yarn satisfies the following i).about.iii) characteristics, after it has been treated for 3 minutes at temperature of 240.degree.0 C., tension of 0.1 g/d, said yarn satisfies the following iv).about.vii) variations of mircrostructural physical properties: i) a density of 1.38.about.1.39 g/cm.sup.3, ii) a birefringence index in amorphous portions of 0.06.about.0.09, iii) tan .delta. peak temperature of 140 .degree. C. and below, iv) the increment of a percent crystallinity (.DELTA.X.sub.c) of 10.about.20 wt. %, v) the decrement of an amorphous orientation coefficient (.DELTA.F.sub.a) of at least 0.05, vi) the increment of a long period value (.DELTA.LP) of at least 10.ANG.