Patents by Inventor Duke C. Hong
Duke C. Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11960429Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address.Type: GrantFiled: December 15, 2022Date of Patent: April 16, 2024Assignee: Intel CorporationInventors: Patrick Connor, Matthew A. Jared, Duke C. Hong, Elizabeth M. Kappler, Chris Pavlas, Scott P. Dubal
-
Publication number: 20230176987Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address.Type: ApplicationFiled: December 15, 2022Publication date: June 8, 2023Inventors: Patrick Connor, Matthew A. JARED, Duke C. HONG, Elizabeth M. KAPPLER, Chris Pavlas, Scott P. Dubal
-
Patent number: 11593292Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address.Type: GrantFiled: June 5, 2020Date of Patent: February 28, 2023Assignee: Intel CorporationInventors: Patrick Connor, Matthew A. Jared, Duke C. Hong, Elizabeth M. Kappler, Chris Pavlas, Scott P. Dubal
-
Publication number: 20200301864Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address.Type: ApplicationFiled: June 5, 2020Publication date: September 24, 2020Applicant: INTEL CORPORATIONInventors: Patrick Connor, Matthew A. Jared, Duke C. Hong, Elizabeth M. Kappler, Chris Pavlas, Scott P. Dubal
-
Patent number: 10684973Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address.Type: GrantFiled: August 30, 2013Date of Patent: June 16, 2020Assignee: Intel CorporationInventors: Patrick Connor, Matthew A. Jared, Duke C. Hong, Elizabeth M. Kappler, Chris Pavlas, Scott P. Dubal
-
Publication number: 20180091447Abstract: Technologies for dynamically transitioning network traffic host buffers of a network computing device include the software abstraction of one or more hardware queues of the network computing device based on a network flow type associated with network traffic received by the network computing device. The network computing device is configured to identify a queue transition event, completing pending transactions in one or more of the software abstracted queues, and transition the abstracted queues to handle the flow type associated with the queue transition event.Type: ApplicationFiled: September 23, 2016Publication date: March 29, 2018Inventors: Matthew A. Jared, Duke C. Hong, Manasi Deval
-
Patent number: 9471350Abstract: Methods, apparatus, software, and system architectures for supporting virtualized system migrations and scaling. Under aspects of a method, data is automatically collected and aggregated at multiple levels by a plurality of agents for each of multiple data centers. The data includes data relating to virtual machine utilization, data relating to electrical utilization costs, data relating to data center utilization, and data relating to triggers events. The data is processed to determine whether to migrate virtual servers from a first data center to a second data center. The software architecture includes a plurality of modules including a controller, data center profile, transition triggers, power cost profile, and virtual machine package module. The agents are implemented in an agent hierarchy and configured to collect data themselves and/or aggregate data from other agents and provide an API to facilitate access to collected data and agent services.Type: GrantFiled: September 26, 2013Date of Patent: October 18, 2016Assignee: Intel CorporationInventors: Chris Pavlas, Duke C. Hong, Scott P. Dubal, Elizabeth M. Kappler, Patrick Connor, Matthew A. Jared
-
Patent number: 9047417Abstract: Methods, apparatus, and computer platforms and architectures employing node aware network interfaces are disclosed. The methods and apparatus may be implemented on computer platforms such as those employing a Non-uniform Memory Access (NUMA) architecture including a plurality of nodes, each node comprising a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a NUMA aware Network Interface Controller (NIC). Under one method, a packet is received from a network at a first NIC comprising a component of a first node, and a determination is made that packet data for the packet is to be forwarded to a second node including a second NIC. The packet data is then forwarded from the first NIC to the second NIC via a NIC-to-NIC interconnect link. Upon being received at the second NIC, processing of the packet (data) is handled as if the packet was received from the network at the second NIC.Type: GrantFiled: October 29, 2012Date of Patent: June 2, 2015Assignee: Intel CorporationInventors: Patrick Conner, Chris Pavlas, Elizabeth M. Kappler, Matthew A. Jared, Duke C. Hong, Scott P. Dubal
-
Publication number: 20150088586Abstract: Methods, apparatus, software, and system architectures for supporting virtualized system migrations and scaling. Under aspects of a method, data is automatically collected and aggregated at multiple levels by a plurality of agents for each of multiple data centers. The data includes data relating to virtual machine utilization, data relating to electrical utilization costs, data relating to data center utilization, and data relating to triggers events. The data is processed to determine whether to migrate virtual servers from a first data center to a second data center. The software architecture includes a plurality of modules including a controller, data center profile, transition triggers, power cost profile, and virtual machine package module. The agents are implemented in an agent hierarchy and configured to collect data themselves and/or aggregate data from other agents and provide an API to facilitate access to collected data and agent services.Type: ApplicationFiled: September 26, 2013Publication date: March 26, 2015Inventors: Chris Pavlas, Duke C. Hong, Scott P. Dubal, Elizabeth M. Kappler, Patrick Connor, Matthew A. Jared
-
Publication number: 20150067229Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address.Type: ApplicationFiled: August 30, 2013Publication date: March 5, 2015Inventors: Patrick Connor, Matthew A. Jared, Duke C. Hong, Elizabeth M. Kappler, Chris Pavlas, Scott P. Dubal
-
Publication number: 20140122634Abstract: Methods, apparatus, and computer platforms and architectures employing node aware network interfaces are disclosed. The methods and apparatus may be implemented on computer platforms such as those employing a Non-uniform Memory Access (NUMA) architecture including a plurality of nodes, each node comprising a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a NUMA aware Network Interface Controller (NIC). Under one method, a packet is received from a network at a first NIC comprising a component of a first node, and a determination is made that packet data for the packet is to be forwarded to a second node including a second NIC. The packet data is then forwarded from the first NIC to the second NIC via a NIC-to-NIC interconnect link. Upon being received at the second NIC, processing of the packet (data) is handled as if the packet was received from the network at the second NIC.Type: ApplicationFiled: October 29, 2012Publication date: May 1, 2014Inventors: Patrick Conner, Chris Pavlas, Elizabeth M. Kappler, Matthew A. Jared, Duke C. Hong, Scott P. Dubal