Patents by Inventor Duke T. Tran

Duke T. Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030038681
    Abstract: A voltage controlled oscillator in a clock multiply unit includes a plurality of varactors controlled by a plurality of respective control voltage signals. The plurality of varactors allows for a combination of efficient methods to set an output signal frequency for the voltage controlled oscillator. For example, a pair of independent varactors are controlled by a differential control voltage signal. Differential control improves noise immunity and fine tuning ranges of the voltage controlled oscillator. The voltage controlled oscillator determines an operating frequency range automatically at start-up or upon reset.
    Type: Application
    Filed: June 4, 2001
    Publication date: February 27, 2003
    Inventors: Masoud Djafari, Duke T. Tran, Syed K. Enam
  • Publication number: 20020118006
    Abstract: A phase frequency detector in a clock multiply unit of a serial transmitter detects differences in phase and frequency between a reference clock and an internal clock generated by the clock multiply unit. The phase frequency detector includes a reset circuit which increases the sensitivity and reliability of the phase frequency detector, thereby allowing the phase frequency detector to operate at high speeds. The phase frequency detector produces a pair of output signals which have rising edges corresponding to rising edges of the reference clock and the internal clock respectively. The reset circuit activates a reset signal to reset the phase frequency detector when the output signals are both at logic high and continues to activate the reset signal until both of the output signals reach logic low.
    Type: Application
    Filed: June 4, 2001
    Publication date: August 29, 2002
    Inventors: Syed K. Enam, Masoud Djafari, Duke T. Tran
  • Publication number: 20020109552
    Abstract: A voltage controlled oscillator in a clock multiply unit includes a plurality of varactors controlled by a plurality of respective control voltage signals. The plurality of varactors allows for a combination of efficient methods to set an output signal frequency for the voltage controlled oscillator. For example, a pair of independent varactors are controlled by a differential control voltage signal. Differential control improves noise immunity and fine tuning ranges of the voltage controlled oscillator. The voltage controlled oscillator determines an operating frequency range automatically at start-up or upon reset.
    Type: Application
    Filed: June 4, 2001
    Publication date: August 15, 2002
    Inventors: Duke T. Tran, Syed K. Enam, Masoud Djafari
  • Publication number: 20020109553
    Abstract: A voltage controlled oscillator in a clock multiply unit includes a plurality of varactors controlled by a plurality of respective control voltage signals. The plurality of varactors allows for a combination of efficient methods to set an output signal frequency for the voltage controlled oscillator. For example, a pair of independent varactors are controlled by a differential control voltage signal. Differential control improves noise immunity and fine tuning ranges of the voltage controlled oscillator. The voltage controlled oscillator determines an operating frequency range automatically at start-up or upon reset.
    Type: Application
    Filed: June 4, 2001
    Publication date: August 15, 2002
    Inventors: Duke T. Tran, Syed K. Enam, Masoud Djafari
  • Publication number: 20020097682
    Abstract: The invention relates to methods and apparatus that provide a low frequency data loop-back in a transceiver to advantageously provide built-in test capability with low overhead. The low frequency loop-back advantageously allows testing of a receiver and a transmitter of the transceiver through a high frequency serial interface while reducing the need to interface to a low frequency interface of the transceiver with expensive and specialized test equipment. One embodiment of the low frequency data loop-back includes a transceiver configured to select between a reference clock signal for normal use of the transceiver and a clock signal generated from serial data for test use in response to an activation of a loop-back test command. In one embodiment, a multiplexer selects between the reference clock signal and the generated clock signal.
    Type: Application
    Filed: June 4, 2001
    Publication date: July 25, 2002
    Inventors: Syed K. Enam, Masoud Djafari, Duke T. Tran, R. Keuf Smythe, Michael B. Choi, Bo-Shiou Ke, Vi Lee