Patents by Inventor Dumitru Nicolae Lesenco

Dumitru Nicolae Lesenco has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10566409
    Abstract: An integrated, quantized inductor, comprising a plurality of identical inductor sections, is provided for multiple applications on the chip. The inductor section represents one turn and includes two stacked metal layers with identical area and configuration, separated by dielectric layers, winding around the insulated ferromagnetic core, and interconnected by via. Power transformer, having a primary winding and multiple secondary windings comprised of a plurality of identical inductor sections and a shielded common ferromagnetic core ring, placed outside of the active chip area between the seal ring and pad-ring enhanced area. Inside of active chip area, in proximity to the related linear RF components are placed sensitive inductors, balun-transformers, resonator, separately protected by EM guard rings, wherein one node is open, and the second one is tied to the ground. The fabrication is compatible with integrated circuits manufacturing.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: February 18, 2020
    Inventors: Dumitru Nicolae Lesenco, Nicolae Dumitru Lesenco
  • Publication number: 20170162559
    Abstract: The present invention relates to vertical integrated, quantized FET with sharp drain and BJT with sharp emitter implemented in one nano-BiCMOS process, using multiple identical single crystalline semiconductor pyramids, placed in-situ directly on the surface of diffusion regions. The devices' gate and base structures are formed at a level of 35-45 nm below the top of the pyramids. The bottom region of the pyramids contains the collector/source structures, while the top region of the pyramids contains the emitter/drain structures. The base structure for BJT is formed by selective epitaxial growth of Si—SixGe1-x—Si with opposite conductivity type as COR, and interconnected by a horizontal polysilicon grid. The self-aligned gate structure for FET is formed by high dopant implantation of impurity with the same type of conductivity as COR through horizontal gate bridge, which represent a grid of horizontal stacked layers Si3N4 —high-k insulator—polysilicon—high-k insulator—Si3N4.
    Type: Application
    Filed: December 7, 2015
    Publication date: June 8, 2017
    Inventor: Dumitru Nicolae Lesenco
  • Publication number: 20160284651
    Abstract: The present invention relates to RFIC process design kits and microelectronics device technologies. More particularly, the invention relates to inductors, transformers, resonators, and electromagnetic (EM) guard rings implemented in one chip. Integrated quantized power transformer, having a primary winding and multiple secondary windings comprised of a plurality of identical inductor sections and with a shielded commune ferromagnetic layer ring, placed outside of the active chip area between the seal ring and pad-ring enhanced area. Inside of active chip area, proximity to the related linear RF components are placed sensitive inductors, balun-transformers, resonators, separately protected by EM guard rings, where each quantized inductor serves as an EM antenna, wherein one node is open, and the second one is tied to the ground.
    Type: Application
    Filed: May 10, 2016
    Publication date: September 29, 2016
    Inventor: Dumitru Nicolae LESENCO
  • Publication number: 20040207309
    Abstract: A flat color display device with carbon thin-film cold cathode field emission is provided for display of information by response to an electron beam of a phosphor coating on a face plate. A color display device is assembled from monolithic display sections on multilayer printed wiring board as active matrix. There is not restriction for maximum display sections number in the horizontal and vertical directions. Each monolithic display section is represented as ball grid array system on a package and is assembled from four separate fabricated parts: bottom support part, control chip, cathode-grid silicon part and anode top part. The interconnect between bottom plate, control chip, cathodes, modulating grid, x-y focusing grids, x-y deflecting grids and anode are implemented throw anisotropic etched and insulated holes in silicon cathode-grid part and interlayer vias.
    Type: Application
    Filed: April 21, 2003
    Publication date: October 21, 2004
    Inventor: Dumitru Nicolae Lesenco