Abstract: The invention relates to a tuning memory device for tuning circuits to selectable frequencies and in which digital tuning data corresponding to said frequencies are stored in a programmable memory. For each selectable frequency the programmable memory contains an information element indicating whether writing said line has been effected correctly. A logic frequency-selection circuit includes a buffer register (REG) receiving address data from a BUS, which data are loaded in an up/down counter UP/DN, and a shift register L.sub.1 . . . L.sub.n which is clocked by a clock signal (MW,CR). Each time a defective row of the memory is detected (signal BLD), the up/down counter UPDN is decremented by one unit so a defective row is not counted. When the up/down counter reaches a predetermined count, identified by a gate 40, the shift register is positioned to the desired row corresponding to the selected frequency and addresses via the output of a corresponding register multivibrator (L.sub.1 . . . L.sub.