Abstract: A bonding structure that may be used to form 3D-IC devices is formed using first oblong bonding pads on a first substrate and second oblong bonding pads one a second substrate. The first and second oblong bonding pads are laid crosswise, and the bond is formed. Viewed in a first cross-section, the first bonding pad is wider than the second bonding pad. Viewed in a second cross-section at a right angle to the first, the second bonding pad is wider than the first bonding pad. Making the bonding pads oblong and angling them relative to one another reduces variations in bonding area due to shifts in alignment between the first substrate and the second substrate. The oblong shape in a suitable orientation may also be used to reduce capacitive coupling between one of the bonding pads and nearby wires.

Abstract: A semiconductor structure includes a substrate, a conductive via and a first insulation layer. The conductive via is through the substrate. The first insulation layer is between the substrate and the conductive via. A first surface of the first insulation layer facing the substrate and a second surface of the first insulation layer facing the conductive via are extended along different directions.

Abstract: Methods and devices of having an enclosure structure formed in a multi-layer interconnect and a through-silicon-via (TSV) extending through the enclosure structure. In some implementations, a protection layer is formed between the enclosure structure and the TSV.

Abstract: Some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. The extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. Because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. The extended via finds application for capacitor arrays used for pixel circuits.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor including first chip and a second chip. The first chip includes a first substrate, a plurality of photodetectors disposed in the first substrate, a first interconnect structure disposed on a front side of the first substrate, and a first bond structure disposed on the first interconnect structure. The second chip underlies the first chip. The second chip includes a second substrate, a plurality of semiconductor devices disposed on the second substrate, a second interconnect structure disposed on a front side of the second substrate, and a second bond structure disposed on the second interconnect structure. A first bonding interface is disposed between the second bond structure and the first bond structure. The second interconnect structure is electrically coupled to the first interconnect structure by way of the first and second bond structures.

Abstract: A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.

Abstract: Various embodiments of the present disclosure are directed towards a stacked complementary metal-oxide semiconductor (CMOS) image sensor in which a pixel sensor spans multiple integrated circuit (IC) chips and is devoid of a shallow trench isolation (STI) structure at a photodetector of the pixel sensor. The photodetector and a first transistor form a first portion of the pixel sensor at a first IC chip. A plurality of second transistors forms a second portion of the pixel sensor at a second IC chip. By omitting the STI structure at the photodetector, a doped well surrounding and demarcating the pixel sensor may have a lesser width than it would otherwise have. Hence, the doped well may consume less area of the photodetector. This, in turn, allows enhanced scaling down of the pixel sensor.

Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.

Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a first wafer including a plurality of electronic integrated circuits (EICs), forming a second wafer including a plurality of photonic integrated circuits (PICs), bonding the first wafer to the second wafer to form a first stacked wafer. The bonding of the first wafer to the second wafer includes vertically aligning each of the plurality of the EICs with one of the plurality of the PICs.

Abstract: An image sensor includes a pixel and an isolation structure. The pixel includes a photosensitive region and a circuitry region next to the photosensitive region. The isolation structure is located over the pixel, where the isolation structure includes a conductive grid and a dielectric structure covering a sidewall of the conductive grid, and the isolation structure includes an opening or recess overlapping the photosensitive region. The isolation structure surrounds a peripheral region of the photosensitive region.

Abstract: Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) DoP image sensor and a method for forming the SOI DoP image sensor. In some embodiments, a semiconductor substrate comprises a floating node and a collector region. A photodetector is in the semiconductor substrate and is defined in part by a collector region. A transfer transistor is over the semiconductor substrate. The collector region and the floating node respectively define source/drain regions of the transfer transistor. A semiconductor mesa is over and spaced from the semiconductor substrate. A readout transistor is on and partially defined by the semiconductor mesa. The semiconductor mesa is between the readout transistor and the semiconductor substrate. A via extends from the floating node to a gate electrode of the readout transistor.

Abstract: Provided is a method of fabricating an image sensor device. An exemplary includes forming a plurality of radiation-sensing regions in a substrate. The substrate has a front surface, a back surface, and a sidewall that extends from the front surface to the back surface. The exemplary method further includes forming an interconnect structure over the front surface of the substrate, removing a portion of the substrate to expose a metal interconnect layer of the interconnect structure, and forming a bonding pad on the interconnect structure in a manner so that the bonding pad is electrically coupled to the exposed metal interconnect layer and separated from the sidewall of the substrate.

Abstract: A semiconductor device according to the present disclosure includes a semiconductor layer, a plurality of metal isolation features disposed in the semiconductor layer, a metal grid disposed directly over the plurality of metal isolation features, and a plurality of microlens features disposed over the metal grid.

Abstract: Some embodiments relate an integrated circuit (IC) including a first substrate including a plurality of imaging devices. A second substrate is disposed under the first substrate and includes a plurality of logic devices. A first interconnect structure is disposed between the first substrate and the second substrate and electrically couples imaging devices within the first substrate to one another. A second interconnect structure is disposed between the first interconnect structure and the second substrate, and electrically couples logic devices within the second substrate to one another. A bond pad structure is coupled to a metal layer of the second interconnect structure and extends along inner sidewalls of both the first interconnect structure and the second interconnect structure. An oxide layer extends from above the first substrate to below a plurality of metal layers of the first interconnect structure, and lines inner sidewalls of the bond pad structure.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a plurality of photodetectors disposed within a substrate. The photodetectors are disposed respectively within a plurality of pixel regions. A floating diffusion node is disposed along a front-side surface of the substrate at a middle region of the plurality of pixel regions. A plurality of well regions is disposed within the substrate at corners of the plurality of pixel regions. An isolation structure extends into a back-side surface of the substrate. The isolation structure comprises a plurality of elongated isolation components disposed between adjacent pixel regions, a middle isolation component aligned with the floating diffusion node, and multiple peripheral isolation components aligned with the plurality of well regions. The elongated isolation components have a first height and the middle and peripheral isolation components have a second height less than the first height.

Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor comprise a substrate having a first region and a second region. A first gate overlies the first region. A second gate overlies the second region. A deep trench isolation (DTI) structure is in the substrate and laterally between the first region and the second region. A first floating diffusion node is in the first region. A second floating diffusion node is in the second region. An interlayer dielectric (ILD) structure is over the substrate. A dielectric structure is between the ILD structure and the substrate. The dielectric structure is laterally between the first and second floating diffusion nodes. The dielectric structure is laterally spaced from the first and second gates. The dielectric structure overlies the DTI structure. A width of the dielectric structure is greater than a width of the DTI structure.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method includes forming a first dielectric bonding layer over a first dielectric structure, which is disposed on a first substrate and surrounds a first plurality of interconnects. The first dielectric bonding layer is patterned to form a first recess exposing one of the first plurality of interconnects. A first conductive bonding segment is formed within the first recess. A second dielectric bonding layer is formed over a TSV extending through a second substrate. The second dielectric bonding layer is patterned to form a second recess exposing the TSV. A second conductive bonding segment is formed within the second recess. The first substrate is bonded to the second substrate along an interface comprising dielectric and conductive regions. The conductive region includes a conductive interface between the first and second conductive bonding segments.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first inter-metal dielectric (IMD) structure disposed over a semiconductor substrate. A metal-insulator-metal (MIM) device is disposed over the first IMD structure. The MIM device includes at least three metal plates that are spaced from one another. The MIM device further includes a plurality of capacitor insulator structures. Each of the plurality of capacitor insulator structures are disposed between and electrically isolate neighboring metal plates of the at least three metal plates.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a first chip bonded to a second chip. The first chip includes a semiconductor substrate. The first chip includes a first transistor cell and a second transistor cell. The second transistor cell is laterally spaced from the first transistor cell. A first through-substrate via (TSV) extends vertically through the semiconductor substrate. The first transistor cell is electrically coupled to the first TSV. A second TSV extends vertically through the first semiconductor substrate. The second transistor cell is electrically coupled to the second TSV. The second chip comprises a first readout circuit that is electrically coupled to the first TSV and the second TSV. The first readout circuit is disposed laterally between the first TSV and the second TSV. The first readout circuit is configured to receive a first signal from the first transistor cell.