Patents by Inventor Dun-Nian Yaung

Dun-Nian Yaung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12224298
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip in which a bond pad structure extends to a columnar structure with a high via density. For example, an interconnect structure is on a frontside of a substrate and comprises a first bond wire, a second bond wire, and bond vias forming the columnar structure. The bond vias extend from the first bond wire to the second bond wire. The bond pad structure is inset into a backside of the substrate, opposite the frontside, and extends to the first bond wire. A projection of the first or second bond wire onto a plane parallel to a top surface of the substrate has a first area, and a projection of the bond vias onto the plane has a second area that is 10% or more of the first area, such that via density is high.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: February 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hsien Li, Yen-Ting Chiang, Shyh-Fann Ting, Jen-Cheng Liu, Dun-Nian Yaung
  • Publication number: 20250048658
    Abstract: In some embodiments, the present disclosure relates to an integrated device, including a substrate; an interconnect structure disposed over the substrate, the interconnect structure including an dielectric; a first bottom electrode structure disposed in the dielectric, the first bottom electrode structure having a first width as measured between outer sidewalls of the first bottom electrode structure and a first depth as measured from an upper surface of the dielectric; and a second bottom electrode structure disposed in the dielectric and spaced apart from the first bottom electrode structure, the second bottom electrode structure having a second width as measured between outer sidewalls of the second bottom electrode structure and a second depth as measured from the upper surface of the dielectric; where the first width is greater than the second width and the first depth is greater than the second depth.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 6, 2025
    Inventors: Meng-Hsien Lin, Hsing-Chih Lin, Wei-Chih Weng, Kuan-Hua Lin, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 12218165
    Abstract: An image sensor includes a substrate including a first surface and a second surface opposite to the first surface; a plurality of pixel sensors disposed in the substrate, a sensor isolation feature disposed in the substrate defining an active region, and a dielectric layer between the sensor isolation feature and the substrate, wherein the sensor isolation feature comprises a conductive material.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Hsing-Chih Lin, Che-Wei Chen
  • Patent number: 12218106
    Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Yi-Shin Chu, Ping-Tzu Chen, Che-Wei Chen
  • Patent number: 12218164
    Abstract: A semiconductor image sensing structure includes a substrate having a first region and a second region, a metal grid in the first region, and a hybrid metal shield in the second region. The hybrid metal shield includes a first metallization layer, a second metallization layer disposed over the first metallization layer, a third metallization layer disposed over the second metallization layer, and a fourth metallization layer disposed over the third metallization layer. An included angle of the second metallization layer is between approximately 40° and approximately 60°.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Hsien Yang, Wen-I Hsu, Kuan-Fu Lu, Feng-Chi Hung, Jen-Cheng Liu, Dun-Nian Yaung, Chun-Hao Chou, Kuo-Cheng Lee
  • Patent number: 12218166
    Abstract: A metal grid within a trench isolation structure on the back side of an image sensor is coupled to a contact pad so that a voltage on the metal grid is continuously variable with a voltage on the contact pad. One or more conductive structures directly couple the metal grid to a contact pad. The conductive structures may bypass a front side of the image sensor. A bias voltage on the metal grid may be varied through the contact pad whereby a trade-off between reducing cross-talk and increasing quantum efficiency may be adjusted dynamically in accordance with the application of the image sensor, its environment of use, or its mode of operation.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Wen-Chang Kuo, Shih-Han Huang
  • Patent number: 12211876
    Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate having sidewalls that form one or more trenches. The one or more trenches are disposed along opposing sides of a photodiode and vertically extend from an upper surface of the semiconductor substrate to within the semiconductor substrate. A doped region is arranged along the upper surface of the semiconductor substrate and along opposing sides of the photodiode. A first dielectric lines the sidewalls of the semiconductor substrate and the upper surface of the semiconductor substrate. A second dielectric lines sidewalls and an upper surface of the first dielectric. The doped region has a width laterally between a side of the photodiode and a side of the first dielectric. The width of the doped region varies at different heights along the side of the photodiode.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Jhy-Jyi Sze, Shyh-Fann Ting, Tzu-Jui Wang, Yen-Ting Chiang, Yu-Jen Wang, Yuichiro Yamashita
  • Patent number: 12205868
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first via disposed within a dielectric structure on a substrate, and a second via disposed within the dielectric structure and laterally separated from the first via by the dielectric structure. The first via has a first width that is smaller than a second width of the second via. An interconnect wire vertically contacts the second via and extends laterally past an outermost sidewall of the second via. A through-substrate via (TSV) is arranged over the second via and extends through the substrate. The TSV has a minimum width that is smaller than the second width of the second via. The second via has opposing outermost sidewalls that are laterally outside of the TSV.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: January 21, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Yi-Shin Chu, Ping-Tzu Chen
  • Publication number: 20250022912
    Abstract: An embodiment high-density capacitor includes a bottom electrode having a plurality of non-concentric cylindrical portions, a top electrode including a plurality of vertical portions and a surrounding portion, and a dielectric layer separating the top electrode from the bottom electrode. Each of the plurality of non-concentric cylindrical portions includes an inner shell and an outer shell and each of the plurality of vertical portions is vertically surrounded by the inner shell of a respective cylindrical portion of the bottom electrode. The surrounding portion of the top electrode respectively vertically surrounds each of the plurality of non-concentric cylindrical portions of the bottom electrode such that adjacent non-concentric cylindrical portions of the bottom electrode are separated from one another by the surrounding portion of the top electrode. At least some of the plurality of non-concentric cylindrical portions of the bottom electrode include a spatial distribution having a hexagonal symmetry.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 16, 2025
    Inventors: Meng-Hsien Lin, Dun-Nian Yaung, Jen-Cheng Liu, Hsing-Chih Lin, Ko Chun Liu
  • Publication number: 20250014987
    Abstract: An integrated chip including a semiconductor substrate having a first side and a second side, opposite the first side. A first transistor and a second transistor are along the first side of the semiconductor substrate. A dielectric structure including a plurality of dielectric layers is under the first side of the semiconductor substrate. A first metal line is within the dielectric structure. A second metal line is within the dielectric structure and under the first metal line. A first metal via extends between the first metal line and the second metal line. A through-substrate via (TSV) extends from the second side of the semiconductor substrate, through the semiconductor substrate between the first transistor and the second transistor, to the first metal line and the second metal line.
    Type: Application
    Filed: July 3, 2023
    Publication date: January 9, 2025
    Inventors: Chieh-En Chen, Chen-Hsien Lin, Shyh-Fann Ting, Hsing-Chih Lin, Dun-Nian Yaung
  • Publication number: 20250015124
    Abstract: Fabricating a metal-insulator-metal (MIM) capacitor structure includes: forming a patterned metallization layer; disposing a dielectric material on the patterned metallization layer; etching one or more deep trenches through the dielectric material to the patterned metallization layer; depositing a MIM multilayer on the dielectric material and inside the one or more deep trenches formed in the dielectric material; and fabricating at least one three-dimensional MIM (3D-MIM) capacitor comprising a portion of the MIM multilayer deposited inside at least one of the one or more deep trenches; and fabricating at least one second capacitor, including at least one shallow 3D-MIM capacitor comprising a portion of the MIM multilayer deposited inside one or more shallow trenches passing partway through the dielectric material that are shallower than the one or more deep trenches, and/or at least one two-dimensional MIM (2D-MIM) capacitor comprising a portion of the MIM multilayer deposited on the dielectric material.
    Type: Application
    Filed: July 7, 2023
    Publication date: January 9, 2025
    Inventors: Chieh-En Chen, Chen-Hsien Lin, Shyh-Fann Ting, Wei-Chih Weng, Hsing-Chih Lin, Dun-Nian Yaung
  • Patent number: 12191336
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a deep trench isolation (DTI) structure disposed in a substrate. A pixel region of the substrate is disposed within an inner perimeter of the DTI structure. A photodetector is disposed in the pixel region of the substrate. A gate electrode structure overlies, at least partially, the pixel region of the substrate. A first gate dielectric structure partially overlies the pixel region of the substrate. A second gate dielectric structure partially overlies the pixel region of the substrate. The gate electrode structure overlies both a portion of the first gate dielectric structure and a portion of the second gate dielectric structure. The first gate dielectric structure has a first thickness. The second gate dielectric structure has a second thickness that is greater than the first thickness.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: January 7, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Jui Wang, Dun-Nian Yaung, Chen-Jong Wang, Ming-Chieh Hsu, Wei-Cheng Hsu, Yuichiro Yamashita
  • Publication number: 20250006762
    Abstract: An optical device and a method of fabricating the same are disclosed. The optical device includes a first die layer and a second die layer. The first die layer includes a first substrate having a first surface and a second surface opposite to the first surface, first and second pixel structures, an inter-pixel isolation structure disposed in the first substrate and surrounding the first and second pixel structures, and a floating diffusion region disposed in the first substrate and between the first and second pixel structures. The second die layer includes a second substrate having a third surface and a fourth surface opposite to the third surface and a pixel transistor group disposed on the third surface of the second substrate and electrically connected to the first and second pixel structures.
    Type: Application
    Filed: January 12, 2024
    Publication date: January 2, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh CHUANG, Hsin-Hung CHEN, Wen-I HSU, Peng-Chieh CHIN, Feng-Chi HUNG, Ming-En CHEN, Jen-Cheng LIU, Dun-Nian YAUNG
  • Publication number: 20240429129
    Abstract: Some implementations herein provide a semiconductor device and methods for forming the semiconductor device. A multi-layer structure of the semiconductor device includes a metal ring structure and a dielectric sidewall structure along interior sidewalls of the metal ring structure. An interconnect structure (e.g., a through silicon via interconnect structure) is along a central interior axis of the metal ring structure. A protective layer is between the interconnect structure and the dielectric sidewall structure. During a deposition operation that fills a cavity with a conductive material to form the interconnect structure, the protective layer may protect the dielectric sidewall structure from damage to improve a quality and/or a reliability of the semiconductor device.
    Type: Application
    Filed: June 23, 2023
    Publication date: December 26, 2024
    Inventors: Min-Feng KAO, Shyh-Fann TING, Chen-Hsien LIN, Dun-Nian YAUNG
  • Patent number: 12176370
    Abstract: Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. A conductive feature is disposed over a front side of the semiconductor substrate. A through substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive feature. The through substrate via is laterally offset from the backside isolation structure. A conductive bridge is disposed beneath the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through substrate via.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: December 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Wen-Chang Kuo, Sheng-Chau Chen, Feng-Chi Hung, Sheng-Chan Li
  • Publication number: 20240421177
    Abstract: Provided is a method of fabricating an image sensor device. An exemplary includes forming a plurality of radiation-sensing regions in a substrate. The substrate has a front surface, a back surface, and a sidewall that extends from the front surface to the back surface. The exemplary method further includes forming an interconnect structure over the front surface of the substrate, removing a portion of the substrate to expose a metal interconnect layer of the interconnect structure, and forming a bonding pad on the interconnect structure in a manner so that the bonding pad is electrically coupled to the exposed metal interconnect layer and separated from the sidewall of the substrate.
    Type: Application
    Filed: February 12, 2024
    Publication date: December 19, 2024
    Inventors: Shuang-Ji Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Wen-De Wang, Hsiao-Hui Tseng
  • Publication number: 20240395843
    Abstract: An image sensor includes a pixel and an isolation structure. The pixel includes a photosensitive region and a circuitry region next to the photosensitive region. The isolation structure is located over the pixel, where the isolation structure includes a conductive grid and a dielectric structure covering a sidewall of the conductive grid, and the isolation structure includes an opening or recess overlapping the photosensitive region. The isolation structure surrounds a peripheral region of the photosensitive region.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 28, 2024
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Wen-Chang Kuo, Sheng-Chau Chen, Feng-Chi Hung, Sheng-Chan Li
  • Patent number: 12154939
    Abstract: The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: November 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Sheng Chu, Dun-Nian Yaung, Yu-Cheng Tsai, Meng-Hsien Lin, Ching-Chung Su, Jen-Cheng Liu, Wen-De Wang, Guan-Hua Chen
  • Patent number: 12154927
    Abstract: A semiconductor structure includes a semiconductor substrate, an interconnection structure, a color filter, and a first isolation structure. The semiconductor substrate includes a first surface and a second surface opposite to the first surface. The interconnection structure is disposed over the first surface, and the color filter is disposed over the second surface. The first isolation structure includes a bottom portion, an upper portion and a diffusion barrier layer surrounding a sidewall of the upper portion. A top surface of the upper portion of the first isolation structure extends into and is in contact with a dielectric layer of the interconnection structure.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yen-Ting Chiang, Chun-Yuan Chen, Hsiao-Hui Tseng, Sheng-Chan Li, Yu-Jen Wang, Wei Chuang Wu, Shyh-Fann Ting, Jen-Cheng Liu, Dun-Nian Yaung
  • Publication number: 20240387613
    Abstract: The present disclosure, in some embodiments, relates to a capacitor structure. The capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A lower electrode is arranged along sidewalls and an upper surface of the lower dielectric structure, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is arranged along outermost sidewalls of the upper electrode. The spacer includes a first upper surface arranged along a first side of the upper electrode and a second upper surface arranged along an opposing second side of the upper electrode. The first upper surface has a different width than the second upper surface.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 21, 2024
    Inventors: Ching-Sheng Chu, Dun-Nian Yaung, Yu-Cheng Tsai, Meng-Hsien Lin, Ching-Chung Su, Jen-Cheng Liu, Wen-De Wang, Guan-Hua Chen