Abstract: A method includes bonding a first semiconductor chip on a second semiconductor chip, applying an etching process to the first semiconductor chip and the second semiconductor chip until a metal surface of the second semiconductor chip is exposed, wherein as a result of applying the etching process, an opening is formed in the first semiconductor chip and the second semiconductor chip and plating a conductive material in the opening to from a conductive plug.

Abstract: A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die, and a second semiconductor die bonded on the first semiconductor die. A through-substrate via penetrates through a semiconductor substrate of the second semiconductor die. A passivation layer is disposed between the first semiconductor die and the second semiconductor die, wherein the passivation layer is directly bonded to the semiconductor substrate of the second semiconductor die. A conductive feature passes through the passivation layer, wherein the conductive feature is bonded to the through-substrate via. A barrier layer is disposed between the conductive feature and the passivation layer. The barrier layer covers sidewalls of the conductive feature and separates the surface of the conductive feature from a nearest neighboring surface of the first or second semiconductor die.

Abstract: A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.

Abstract: The present disclosure, in some embodiments, relates to a semiconductor device. The semiconductor device has a gate stack arranged over a first surface of a substrate. A doped isolation feature is arranged within the substrate along opposing sides of the gate stack. A photodetector is also arranged within the substrate. An isolation well region extends below the gate stack and contacts the doped isolation feature along a horizontal plane that is parallel to the first surface and that intersects sides of the photodetector.

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a first IC die comprises a first bonding structure and a first interconnect structure over a first semiconductor substrate. A second IC die is disposed over the first IC die and comprises a second bonding structure and a second interconnect structure over a second semiconductor substrate. A seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate. A plurality of through silicon via (TSV) coupling structures is arranged in the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure and closer to the 3D IC than the seal-ring structure. The plurality of TSV coupling structures respectively comprises a TSV disposed in the second semiconductor substrate and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias.

Abstract: A method for manufacturing an image sensing device includes forming an interconnection layer over a front surface of a semiconductor substrate. A trench is formed to extend from a back surface of the semiconductor substrate. An etch stop layer is formed along the trench. A buffer layer is formed over the etch stop layer. An etch process is performed for etching the buffer layer. The buffer layer and the etch stop layer include different materials.

Abstract: The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within a substrate and respectively comprising a photodiode. The photodiode comprises a doped layer with a first doping type and an adjoining region of the substrate with a second doping type that is different than the first doping type. A boundary deep trench isolation (BDTI) structure is disposed between adjacent pixel regions. A multiple deep trench isolation (MDTI) structure overlies the doped layer of the photodiode. The MDTI structure comprises a stack of dielectric layers lining sidewalls of a MDTI trench. A plurality of color filters is disposed at the back-side of the substrate corresponding to the respective photodiode of the plurality of pixel regions and overlying the MDTI structure.

Abstract: Present disclosure provides a semiconductor structure, including a semiconductor substrate having an active side, an interconnect layer in proximity to the active side of the semiconductor substrate, and a through substrate via extending from the semiconductor substrate to a first metal layer of the interconnect layer. The TSV being wider than the continuous metal feature. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. The first bonding structure contacts a first interconnect structure of the first IC die and a second interconnection structure of the second IC die, and has a first portion and a second portion hybrid bonded together. A third IC die is bonded to the second IC die by a third bonding structure. The third bonding structure comprises a second TSV (through substrate via) disposed through the second substrate of the second IC die and includes varies bonding structures according to varies embodiments of the invention.

Abstract: An image sensor is disclosed. The image sensor includes an epitaxial layer, a plurality of plug structures and an interconnect structure. Wherein the plurality of plug structures are formed in the epitaxial layer, and each plug structure has doped sidewalls, the epitaxial layer and the doped sidewalls form a plurality of photodiodes, the plurality of plug structures are used to separate adjacent photodiodes, and the epitaxial layer and the doped sidewalls are coupled to the interconnect structure via the plug structures. An associated method of fabricating the image sensor is also disclosed. The method includes: providing a substrate having a first-type doped epitaxial substrate layer on a second-type doped epitaxial substrate layer; forming a plurality of isolation trenches in the first-type doped epitaxial substrate layer; forming a second-type doped region along sidewalls and bottoms of the plurality of isolation trenches; and filling the plurality of isolation trenches by depositing metal.

Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die, and a second semiconductor die bonded on the first semiconductor die. A through-substrate via penetrates through a semiconductor substrate of the second semiconductor die. A passivation layer is disposed between the first semiconductor die and the second semiconductor die, wherein the passivation layer is directly bonded to the semiconductor substrate of the second semiconductor die. A conductive feature passes through the passivation layer, wherein the conductive feature is bonded to the through-substrate via. A barrier layer is disposed between the conductive feature and the passivation layer. The barrier layer covers sidewalls of the conductive feature and separates the surface of the conductive feature from a nearest neighboring surface of the first or second semiconductor die.

Abstract: Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) DoP image sensor and a method for forming the SOI DoP image sensor. In some embodiments, a semiconductor substrate comprises a floating node and a collector region. A photodetector is in the semiconductor substrate and is defined in part by a collector region. A transfer transistor is over the semiconductor substrate. The collector region and the floating node respectively define source/drain regions of the transfer transistor. A semiconductor mesa is over and spaced from the semiconductor substrate. A readout transistor is on and partially defined by the semiconductor mesa. The semiconductor mesa is between the readout transistor and the semiconductor substrate. A via extends from the floating node to a gate electrode of the readout transistor.

Abstract: An image-sensor device is provided. The image-sensor device includes a substrate having a front side and a back side. The image-sensor device also includes a radiation-sensing region operable to detect incident radiation that enters the substrate through the back side. The image-sensor device further includes a deep-trench isolation structure extending from the back side towards the front side. The deep-trench isolation structure includes a dielectric layer, and the dielectric layer contains hafnium or aluminum.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first plurality of interconnect layers within a first inter-level dielectric (ILD) structure disposed along a front-side of a first substrate. A conductive pad is arranged along a back-side of the first substrate and a first through-substrate-via (TSV) extends between an interconnect wire of the first plurality of interconnect layers and the conductive pad. A second plurality of interconnect layers are within a second ILD structure disposed along a front-side of a second substrate that is bonded to the first substrate. A second through substrate via (TSV) extends through the second substrate. The second TSV has a greater width than the first TSV.

Abstract: Some embodiments relate an integrated circuit (IC). The IC includes a first substrate including an array of photodetectors, wherein a bond pad opening extends through the first substrate and is defined by an inner sidewall of the first substrate. An interconnect structure is disposed over the first substrate and includes a plurality of metal layers stacked over one another and disposed within a dielectric structure. The bond pad opening further extends through at least a portion of the interconnect structure and is further defined by an inner sidewall of the interconnect structure. A bond pad structure directly contacts a metal layer of the plurality of metal layers in the interconnect structure and is located at an uppermost extent of the bond pad opening.

Abstract: Provided is a method of fabricating an image sensor device. An exemplary includes forming a plurality of radiation-sensing regions in a substrate. The substrate has a front surface, a back surface, and a sidewall that extends from the front surface to the back surface. The exemplary method further includes forming an interconnect structure over the front surface of the substrate, removing a portion of the substrate to expose a metal interconnect layer of the interconnect structure, and forming a bonding pad on the interconnect structure in a manner so that the bonding pad is electrically coupled to the exposed metal interconnect layer and separated from the sidewall of the substrate.

Abstract: A semiconductor device structure includes a first chip, second chip, a first metal structure, a second metal structure, a first via structure and a second via structure. The first chip includes n inter metal dielectric (IMD) layer, which includes different materials adjacent to generate a number of staggered portions having a zigzag configuration. The second chip bonded to the first chip generates a bonding interface. The first metal structure is disposed in the first chip and between the staggered portions and the bonding interface. The first via structure in the first chip stops at the first metal structure. The first via structure includes a first via metal and a first via dielectric layer. A surface roughness of the staggered portions is substantially greater than a surface roughness of the first via dielectric layer. The second via structure extends from the first via structure to the second metal structure.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric structure disposed over a substrate. A plurality of conductive interconnect layers are disposed within the dielectric structure. The plurality of conductive interconnect layers include alternating layers of interconnect wires and interconnect vias. A metal-insulating-metal (MIM) capacitor is arranged within the dielectric structure. The MIM capacitor has a lower conductive electrode separated from an upper conductive electrode by a capacitor dielectric structure. The MIM capacitor vertically extends past two or more of the plurality of conductive interconnect layers.