Abstract: A precorrelation digital spread spectrum receiver includes a signal converter for amplifying and directly converting RF band spread spectrum signals received by an antenna to a digitized baseband signal comprising a sequence of N-bit quantized baseband values. The baseband signal is a linear composite signal containing signals from all satellite channels as well as noise and jamming. An N-bit digital correlator correlates successive N-bit baseband signal values with successive local code values to produce plural correlation signals. A vector processor processes the correlation signals to derive early, late and on-time code correlation signals. The processed correlation signals are accumulated to provide process gain and are used to form error signals for carrier and code tracking, and measurement purposes.A sequential-tracking multi-channel embodiment time shares a common set of circuit elements and digital processing instructions to successively track different channels.

Abstract: A pseudo-random-number code detection and tracking system using a closed loop system wherein a detector having a non-linear response characteristic is responsive to a coded received signal and to a locally generated coded signal to produce an error signal. The error is used to control the characteristics of the local signal so as to cause the signals to become aligned. Means are further provided to dynamically control the non-linear response characteristics of the detector so that the coded received signal and coded local signal remain aligned over a controllable range of error signal levels. Thus, a relatively large range can be used during an acquisition operation and a relatively narrower range during the tracking operation.

Abstract: A pseudo-random-number code detection and tracking system using a closed loop system wherein a detector having a non-linear response characteristic is responsive to a coded received signal and to a locally generated coded signal to produce an error signal. The error is used to control the characteristics of the local signal so as to cause the signals to become aligned. Means are further provided to dynamically control the non-linear response characteristics of the detector so that the coded received signal and coded local signal remain aligned over a controllable range of error signal levels. Thus, a relatively large range can be used during an acquisition operation and a relatively narrower range during the tracking operation.

Abstract: A code tracking signal processing system for tracking a coded signal of the pseudo-random-noise, or PRN, type wherein a time shift comparison is made of the input coded signal and a pair of time estimated coded feedback signals which represent an estimate of the coded input signal which has been advanced and delayed, respectively, by the same specified time shift. An effective error signal is formed from the time shift comparison signals and supplied to a digital integration means, such as an up-down counter, to generate a pair of control signals. The control signals control the pulse rate of a pulsed clock signal in accordance with the time shift error between the estimated code signal and the input code signal. The controlled pulse rate signal is then used to generate the advanced and delayed feedback signals and to produce a coded signal which is in effect locked into time synchronism with the input coded signal.

Abstract: A system for tracking a pair of analog output signals from a resolver wherein such signals are hard-limited to provide square wave representations thereof, such hard limited signals being supplied to at least one digital phase-locked loop in which the phases thereof are compared with those of a pair of square wave digitized feedback signals to produce an error signal. The error signal is digitally integrated to produce a control signal for controllably changing the number of pulses in a pulsed clock signal which is supplied to a feedback counter for producing the pair of feedback signals having phases which are thereby changing so as to minimize the error signal.

Abstract: A phase processing system which includes at least one digital phase-locked loop wherein the phase of the input signal to the loop is compared with the phase of the loop output signal to produce a pulse-width modulated phase error signal. The error signal is digitally integrated, as by a counting means which cyclically counts the pulse widths thereof and provides a first control signal when the count reaches a first value and a second control signal when the count reaches a second value. The control signals are used to control the pulse rate of a clock signal to produce an intermediate clock signal such that when the first control signal is present a pulse is added thereto and when the second control signal is present a pulse is deleted therefrom. The intermediate clock signal is then fed to a feedback divider counting means which provides the loop output signal.

Abstract: A phase processing system which includes at least one digital phase-locked loop wherein the phase of the input signal to the loop is compared with the phase of the loop output signal to produce a pulse-width modulated phase error signal. The error signal is digitally integrated, as by a counting means which cyclically counts the pulse widths thereof and provides a first control signal when the count reaches a first value and a second control signal when the count reaches a second value. The control signals are used to control the pulse rate of a clock signal to produce an intermediate clock signal such that when the first control signal is present a pulse is added thereto and when the second control signal is present a pulse is deleted therefrom. The intermediate clock signal is then fed to a feedback divider counting means which provides the loop output signal.

Abstract: A digital phase-locked loop in which an error signal representing the difference between the phases of an input signal and an output signal is converted to a digital signal having a time-varying value. A programmable divider means is provided to produce a pulse control signal having a frequency which varies in accordance with the time-varying value of the digital signal. The pulse control signal controls the number of pulses which are deleted from a reference clock signal to produce an intermediate signal which in turn is fed to a feedback counter for producing the output signal, the phase of which depends on the number of deleted pulses, so that the phase of the output signal effectively follows the phase of the input signal.