Patents by Inventor Duncan Beadnell

Duncan Beadnell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11709982
    Abstract: The present invention pertains to a method of verifying a design of an integrated circuit. The methods executes an iteration of simulation test cycle using a digital representation of the design. Next, the method obtains simulation results from the iteration of the simulation test cycle and calculates, during the simulation test cycle, a test coverage value associated with the simulation results of the iteration of the simulation test cycle. If the test coverage value is less than a target value, the method determines if the simulation test cycle fails to satisfies an iteration limiting metric. If the simulation test cycle satisfies the iteration limiting metric, the method, dynamically adjusts one or more simulation test cycle parameter during the simulation test cycle and iterates the simulation test cycle and recalculating the test coverage value until the test coverage value is at least the target value or the simulation test cycle fails to satisfy the iteration limiting metric.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: July 25, 2023
    Assignee: Kioxia Corporation
    Inventors: Duncan Beadnell, Francesco Forte
  • Publication number: 20230094798
    Abstract: The present invention pertains to a method of verifying a design of an integrated circuit. The methods executes an iteration of simulation test cycle using a digital representation of the design. Next, the method obtains simulation results from the iteration of the simulation test cycle and calculates, during the simulation test cycle, a test coverage value associated with the simulation results of the iteration of the simulation test cycle. If the test coverage value is less than a target value, the method determines if the simulation test cycle fails to satisfies an iteration limiting metric. If the simulation test cycle satisfies the iteration limiting metric, the method, dynamically adjusts one or more simulation test cycle parameter during the simulation test cycle and iterates the simulation test cycle and recalculating the test coverage value until the test coverage value is at least the target value or the simulation test cycle fails to satisfy the iteration limiting metric.
    Type: Application
    Filed: September 30, 2021
    Publication date: March 30, 2023
    Inventors: Duncan BEADNELL, Francesco FORTE
  • Patent number: 9009440
    Abstract: A storage system stores data in at least one partition of a physical storage media in accordance with file system information specifying a plurality of logical blocks having logical block addresses within the partition. The logical blocks include excess logical blocks that are not mapped to space in the physical storage media by the mapping employed by the storage system. Unusable block data marks those excess logical blocks as unusable. This makes it easy to adjust the data storage capacity of the storage system by changing the mapping to map more or less logical block addresses to space in the physical storage media and thereby destroy or create excess logical blocks, and by changing the unusable block data to correspondingly change the excess logical blocks marked as unusable.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: April 14, 2015
    Assignee: LSI Corporation
    Inventors: Duncan Beadnell, Don Harwood
  • Patent number: 8504755
    Abstract: A bridge device for connecting a USB 3 host device with a plurality of downstream, non-USB 3 mass storage devices, such as SATA or PATA devices. The bridge device comprises an embedded hub having a plurality of internal USB 3 devices. The internal USB 3 devices do not have a physical USB 3 interface. The bridge device also has at least one downstream physical non-USB 3 device, to which a mass storage device may be attached. The internal USB 3 devices enable the host device to be presented with a plurality of USB 3 devices. This, in turn, allows transfer to the plurality of downstream physical non-USB 3 devices, via the internal USB 3 devices at an increased rate. The bridge may also include a downstream physical USB 3 interface. This can allow multiple bridge devices to be connected together in a cascade.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: August 6, 2013
    Assignee: PLX Technology, Inc.
    Inventors: Duncan Beadnell, Neil Buxton, Gary Calder
  • Publication number: 20110219163
    Abstract: A bridge device for connecting a USB 3 host device with a plurality of downstream, non-USB 3 mass storage devices, such as SATA or PATA devices. The bridge device comprises an embedded hub having a plurality of internal USB 3 devices. The internal USB 3 devices do not have a physical USB 3 interface. The bridge device also has at least one downstream physical non-USB 3 device, to which a mass storage device may be attached. The internal USB 3 devices enable the host device to be presented with a plurality of USB 3 devices. This, in turn, allows transfer to the plurality of downstream physical non-USB 3 devices, via the internal USB 3 devices at an increased rate. The bridge may also include a downstream physical USB 3 interface. This can allow multiple bridge devices to be connected together in a cascade.
    Type: Application
    Filed: March 3, 2010
    Publication date: September 8, 2011
    Inventors: Duncan Beadnell, Neil Buxton, Gary Calder
  • Publication number: 20090125699
    Abstract: A storage system stores data in at least one partition of a physical storage media in accordance with file system information specifying a plurality of logical blocks having logical block addresses within the partition. The logical blocks include excess logical blocks that are not mapped to space in the physical storage media by the mapping employed by the storage system. Unusable block data marks those excess logical blocks as unusable. This makes it easy to adjust the data storage capacity of the storage system by changing the mapping to map more or less logical block addresses to space in the physical storage media and thereby destroy or create excess logical blocks, and by changing the unusable block data to correspondingly change the excess logical blocks marked as unusable.
    Type: Application
    Filed: November 12, 2007
    Publication date: May 14, 2009
    Inventors: Duncan Beadnell, Don Harwood