Abstract: A high-density memory device and design method that utilizes some or all of the existing stacked process conductor layers provided by a manufacturing process to enhance the number of available bitlines and/or wordlines within the memory device. The memory device includes a plurality of memory cells arranged in columns and rows, a plurality of wordlines, a plurality of bitlines, at least one via-stack, wherein said existing stacked process conductor layers are used to implement at least one additional wordline or bitline. The via-stacks consist of a plurality of vias, are located close to a memory cell, and adapted to electrically connect the memory cell to multiple bitlines or multiple wordlines or both0. This design method increases the number of possible connections to or from each individual memory cell. When this design method is combined with varied configurations of basic underlying ROM cell types, even further increased cell density can be achieved.

Abstract: A method of operating a digital computer includes the steps of addressing a memory, reading a row of data from the memory, providing the same computational instruction simultaneously to each processor element of a plurality of processor elements, where each of the processor elements is selectively coupled to a corresponding bit position of the memory row of data, performing the same computational operation on a selected plurality of data bits in parallel, and writing the result into the memory at the same row as the data was read from.

Abstract: A method of operating a digital computer includes the steps of addressing a memory, reading a row of data from the memory, providing the same computational instruction simultaneously to each processor element of a plurality of processor elements, where each of the processor elements is selectively coupled to a corresponding bit position of the memory row of data, performing the same computational operation on a selected plurality of data bits in parallel, and writing the result into the memory at the same row as the data was read from.

Abstract: A method of operating a digital computer includes the steps of addressing a memory, reading a row of data from the memory, providing the same computational instruction simultaneously to each processor element of a plurality of processor elements, where each of the processor elements is selectively coupled to a corresponding bit position of the memory row of data, performing the same computational operation on a selected plurality of data bits in parallel, and writing the result into the memory at the same row from which the data was read.

Abstract: An interprocessor communication system is used in a multiprocessor where each processor is simultaneously a transmitter and a receiver of data. A data bus having only two states, a default state and an active state (e.g. high and low levels), is coupled to a plurality of bi-directional bus transceivers. Each transceiver is coupled between a processor element and a data bus and has an enable input. When the transceiver is enabled, it propagates an active level received at one end, either the processor element end or the data bus end, to the other end. The active state dominates on the interprocessor bus, so for instance, when multiple processors transmit, if any processor transmits a low level, then the bus will be low and all processors with enabled transceivers will also receive that low signal. This can be used for broadcasting data or combine operations such as AND or minimum.

Abstract: A digital computer performs read-modify-write (RMW) processing on each bit of a row of memory in parallel, in one operation cycle, comprising: (a) addressing a memory, (b) reading each bit of a row of data from the memory in parallel, (c) performing the same computational operation on each bit of the data in parallel, using an arithmetic logic unit (ALU) in a dedicated processing element, and (d) writing the result of the operation back into the original memory location for each bit in the row.

Abstract: A random access memory chip comprising static random access storage elements, word lines and bit lines connected to the storage elements, a sense amplifier connected to each of the bit lines, a separate processor element connected to each of the sense amplifiers, apparatus for addressing a word line, and apparatus for applying a single instruction to the processor elements, whereby the instructed processor elements are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the addressed word line. A method of operating a digital computer comprising in one operation cycle, addressing a memory, reading each of a row of data from the memory in parallel, and performing an operation function on each bit of the data in parallel to provide a result.

Abstract: A random access memory chip is comprised of static random access storage elements, word lines, and bit lines connected to the storage elements, a sense amplifier connected to each of the bit lines, a separate processor element connected to each of the sense amplifiers, apparatus for addressing a word line, and apparatus for applying a single instruction to the processor elements, whereby the instructed processor elements are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the addressed word line. A method of operating a digital computer is comprised of in one operation cycle, addressing a memory, reading each of a row of data from the memory in parallel, and performing a same operation function on each bit of the data in parallel to provide a result.