Patents by Inventor Duncan Halstead

Duncan Halstead has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for custom design in a standard cell design environment
    Patent number: 6898767
    Abstract: Disclosed is a method for converting a SPICE format circuit description to a standard cell HDL netlist, such as Verilog, allowing simulation and verification in HDL format. SPICE elements may be converted to circuit functions and corresponding standard cells are then selected. The SPICE netlist is employed to define timing paths. Timing information from SPICE simulation is correlated with timing characteristics of the standard cells and a standard delay file is produced such that, when applied to the standard cells, timing approximates that of the SPICE simulation. The present invention may also employ SPICE to Verilog conversion wherein a SPICE netlist is converted to a Verilog standard cell netlist. Timing information from SPICE simulation is correlated with timing characteristics of the standard cells in the Verilog netlist and a standard delay file is produced such that, when applied to the standard cells, timing approximates that of SPICE simulations.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: May 24, 2005
    Assignee: LSI Logic Corporation
    Inventor: Duncan Halstead
  • Method and apparatus for custom design in a standard cell design environment
    Publication number: 20030212967
    Abstract: Disclosed is a method for converting a SPICE format circuit description to a standard cell HDL netlist, such as Verilog, allowing simulation and verification in HDL format. SPICE elements may be converted to circuit functions and corresponding standard cells are then selected. The SPICE netlist is employed to define timing paths. Timing information from SPICE simulation is correlated with timing characteristics of the standard cells and a standard delay file is produced such that, when applied to the standard cells, timing approximates that of the SPICE simulation. The present invention may also employ SPICE to Verilog conversion wherein a SPICE netlist is converted to a Verilog standard cell netlist. Timing information from SPICE simulation is correlated with timing characteristics of the standard cells in the Verilog netlist and a standard delay file is produced such that, when applied to the standard cells, timing approximates that of SPICE simulations.
    Type: Application
    Filed: May 9, 2002
    Publication date: November 13, 2003
    Inventor: Duncan Halstead