Abstract: An alternate multi-thread pipeline structure and method are provided. A deep pipeline is provided in which two threads of two separate pipeline stages are alternatively presented to the various logic and latch circuits for execution. The execution and latching of the threads alternates from one thread to the other within a single clock cycle. Thus, each thread is executed once per clock cycle and two threads are executed in a single clock cycle.

Abstract: According to one embodiment, a RAM array includes at least one RAM cell comprising a first access transistor driven by a first word line. When the first access transistor is turned on, it couples the RAM cell to a first bit line. The first bit line is connected to a single-ended sense amplifier such as an inverter. Similarly, the RAM cell comprises second, third, and fourth access transistors driven by respectively second, third, and fourth word lines. When the respective access transistors are turned on, they couple the RAM cell to respectively second, third, and fourth bit lines. The bit lines are connected to respective single-ended sense amplifiers such as inverters. In one embodiment, each of the first, second, third, and fourth access transistors is an NFET. The first, second, third, and fourth bit lines are coupled to respectively first, second, third, and fourth precharge transistors.

Abstract: A data processing system (10) and associated method (150) of operation selectively compand data on a slot-by-slot basis. The data processing system (10) includes a processor (12), processor bus (14), memory (16), output serial interface (18), and input serial interface (70). The output serial interface (18) includes an output data buffer (20), compression module (22), output shift register (24), and output controller (26). In operation, the output serial interface (18) receives output data (28) and selectively compresses the data on a slot-by-slot basis. The shift register (24) then places the transmit data (32) on the serial link (25). An input serial interface (128) selectively expands data received on the serial link (25) on a slot-by-slot basis to produce input data (82). The associated method (150) includes method steps for companding data on a slot-by-slot basis. An ISDN interface and digital telephone (200) employ the teachings of the present invention.

Abstract: A process for forming a via in a semiconductor device using a self-aligned metal pillar to connect metal layers separated by a dielectric. A first aluminum layer is formed on an oxide layer overlying a semiconductor substrate, and a thin tungsten layer is formed and patterned overlying the first aluminum layer. The pattern in this tungsten layer will determine the pattern for the first level of metal interconnect to be formed later in the first aluminum layer. The tungsten layer is etched using the underlying first aluminum layer as an etch stop. A second aluminum layer is then formed overlying the patterned tungsten layer and the exposed regions of the first aluminum layer. In one continuous etching step the second aluminum layer is patterned and etched to form a pillar, and the first aluminum layer is etched to form the first level of metal interconnect in the semiconductor device using the pattern formed earlier in the tungsten layer and to expose regions of the oxide layer.