Abstract: A method and apparatus for synchronizing a clock between first and second logic blocks (20,21) connected via an asynchronous bus (22). The second logic block includes a clock signal generator (9) responsive to an input synchronizing signal to generate a clock signal synchronized with the synchronizing signal. Data is transferred in blocks from the first logic block (20) to the second logic block (21) across the asynchronous bus (22), the receipt of a data block by the second logic block (21) being used to generate the synchronizing signal.

Abstract: A method and apparatus for synchronizing clock signals on first and second logic blocks connected via an asynchronous bus, wherein the second logic block includes a clock signal generator. The method comprises causing the clock signal on the first logic block to increment a first count; causing the clock signal on the second logic block to increment a second count; comparing the first and second counts; and adjusting the clock signal on the second logic block in response to the result of the comparison to synchronize the two clock signals, wherein the transfer of information between the logic blocks is carried out via the asynchronous bus.