Abstract: Systems and methods are disclosed for operating a core circuitry of an integrated circuit at a lower voltage than the coupled IO circuitry using a tolerant circuit. In one embodiment includes a voltage tolerant circuit comprising a voltage detect module adapted to detect when a voltage is sufficient to switch bias conditions without violating maximum transistor operating conditions and a comparator adapted to detect when a PAD voltage is greater than an IO power supply voltage.

Abstract: Systems and methods are disclosed for reducing or eliminating hot carrier injection stress in circuits. In one embodiment, the present invention relates to an integrated circuit comprising an IO PAD, an output circuit coupled to at least the IO PAD and a stress circuit. The stress circuit is coupled to at least the output circuit and is adapted to limit a high voltage across the output circuit when the output circuit is enabled, thereby reducing stress on the output circuit. In one embodiment, the stress circuit comprises at least one transistor device (a p-channel device or two stacked p-channel devices, for example) and the output circuit comprises a transistor device (an n-channel device or two stacked n-channel devices).

Abstract: Systems and methods are disclosed for operating a core circuitry of an integrated circuit at a lower voltage than the coupled IO circuitry using a tolerant circuit. In one embodiment includes a voltage tolerant circuit comprising a voltage detect module adapted to detect when a voltage is sufficient to switch bias conditions without violating maximum transistor operating conditions and a comparator adapted to detect when a PAD voltage is greater than an IO power supply voltage.

Abstract: Systems and methods are disclosed for operating a core circuitry of an integrated circuit at a lower voltage than the coupled IO circuitry using a tolerant circuit. In one embodiment includes a voltage tolerant circuit comprising a voltage detect module adapted to detect when a voltage is sufficient to switch bias conditions without violating maximum transistor operating conditions and a comparator adapted to detect when a PAD voltage is greater than an IO power supply voltage.

Abstract: Systems and methods are disclosed for operating a core circuitry of an integrated circuit at a lower voltage than the coupled IO circuitry using a tolerant circuit. In one embodiment includes a voltage tolerant circuit comprising a voltage detect module adapted to detect when a voltage is sufficient to switch bias conditions without violating maximum transistor operating conditions and a comparator adapted to detect when a PAD voltage is greater than an IO power supply voltage.

Abstract: Systems and methods are disclosed for reducing or eliminating hot carrier injection stress in circuits. In one embodiment, the present invention relates to an integrated circuit comprising an IO PAD, an output circuit coupled to at least the IO PAD and a stress circuit. The stress circuit is coupled to at least the output circuit and is adapted to limit a high voltage across the output circuit when the output circuit is enabled, thereby reducing stress on the output circuit. In one embodiment, the stress circuit comprises at least one transistor device (a p-channel device or two stacked p-channel devices, for example) and the output circuit comprises a transistor device (an n-channel device or two stacked n-channel devices).

Abstract: A semiconductor device (400) and method are provided for multiplying a capacitance. A contact region (402) is formed in an island in a semiconductor substrate (499) bounded by an isolation region (403), producing the capacitance at the junction of the contact region (402). A dielectric layer (404) is formed over the semiconductor substrate (499) adjacent to the contact region (402). A contact layer (408) is formed over the dielectric layer (404) wherein an inversion layer (406) is formed under the contact layer (408), producing an inversion capacitance in response to an enabling signal. The inversion capacitance corresponds to a multiple of the capacitance.

Abstract: An integrated circuit and method produce a first clock signal (CLOCK) from a reference clock (REFCLK) but at a different frequency. A variable delay line (32) produces the first clock signal by introducing a variable delay in the reference clock signal that is controlled by a programming signal generated in a counter (34). The programming signal is incremented by a second clock signal (UP) while transitions of a fixed delay clock signal lead transitions of the first clock signal. When the programming signal reaches the count of a rollover code (ROLLOVER), the programming signal is reset to a zero count to begin a new sequence. A calibration circuit (36, 38, 40, 42) determines the count of the programming signal needed to produce the rollover code when the variable delay is at least as great as one period of the reference clock signal.

Abstract: A circuit and method are provided for generating a programmable clock signal VRCLK at a frequency of a reference signal VREF such that the phase of VRCLK in relation to the phase of VREF is variable. VREF and VRCLK are each coupled to a frequency comparing circuit which computes their respective frequencies. The frequency comparing circuit subtracts the respective frequencies of VREF and VRCLK to produce a frequency adjusting signal VFREQ which corresponds to the difference in the frequencies of VREF and VRCLK. VFREQ is used to adjust the frequency of VRCLK.

Abstract: An improved Schottky barrier diode for increasing the alpha particle resistance of static random access memories includes an extra implanted N-type region at the surface of the epitaxial layer to increase the impurity concentration there to about 1.times.10.sup.19 atoms per cubic centimeter. In one device, arsenic is employed to overcompensate a guard ring where the Schottky diode is to be formed, while in another device phosphorus is employed and the guard ring is not overcompensated. The resulting Schottky diodes, when employed in the static random access memory cells, dramatically increase the alpha particle resistance of such cells, while also substantially decreasing the access time.