Patents by Inventor Duncan Moss

Duncan Moss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11948053
    Abstract: A computing system, including a processor configured to, at development time, receive a machine learning model topology including a plurality of layers. The processor may be further configured to generate an internal representation graph of the machine learning model topology. The internal representation graph may include a plurality of internal representation layers. By performing one or more modifications to the internal representation graph, the processor may be further configured to generate an inferencer graph including a plurality of inferencer layer blocks. Each inferencer layer block may indicate an input buffer size, a logic function, and an output buffer size. At deployment time, the processor may be further configured to transmit, to a plurality of processing devices, instructions to implement the machine learning model topology with the respective input buffer sizes, logic functions, and output buffer sizes selected for the plurality of inferencer layer blocks of the inferencer graph.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: April 2, 2024
    Assignee: MEGH COMPUTING, INC.
    Inventor: Duncan Moss
  • Patent number: 11405312
    Abstract: A computing system is provided, including a processor configured to receive a directed acyclic graph (DAG) template specifying a data pipeline of a plurality of processing stages. For each processing stage, the processor may be further configured to select a respective processing device of a plurality of communicatively linked processing devices. The processor may be further configured to determine a routing sequence between the plurality of processing devices according to the DAG template. The processor may be further configured to transmit a plurality of input packets encoding the plurality of processing stages to the respective processing devices selected for the processing stages as specified by the routing sequence. In response to transmitting the plurality of input packets, the processor may be further configured to receive, from a processing device of the plurality of processing devices, one or more output packets encoding a processing result of the data pipeline.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: August 2, 2022
    Assignee: MEGH COMPUTING, INC.
    Inventors: Suchit Subhaschandra, Jonathan Beare, Duncan Moss
  • Publication number: 20220092465
    Abstract: A computing system, including a processor configured to, at development time, receive a machine learning model topology including a plurality of layers. The processor may be further configured to generate an internal representation graph of the machine learning model topology. The internal representation graph may include a plurality of internal representation layers. By performing one or more modifications to the internal representation graph, the processor may be further configured to generate an inferencer graph including a plurality of inferencer layer blocks. Each inferencer layer block may indicate an input buffer size, a logic function, and an output buffer size. At deployment time, the processor may be further configured to transmit, to a plurality of processing devices, instructions to implement the machine learning model topology with the respective input buffer sizes, logic functions, and output buffer sizes selected for the plurality of inferencer layer blocks of the inferencer graph.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 24, 2022
    Inventor: Duncan Moss
  • Patent number: 11275998
    Abstract: The present disclosure relates generally to techniques for improving the implementation of certain operations on an integrated circuit. In particular, deep learning techniques, which may use a deep neural network (DNN) topology, may be implemented more efficiently using low-precision weights and activation values by efficiently performing down conversion of data to a lower precision and by preventing data overflow during suitable computations. Further, by more efficiently mapping multipliers to programmable logic on the integrated circuit device, the resources used by the DNN topology to perform, for example, inference tasks may be reduced, resulting in improved integrated circuit operating speeds.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Martin Langhammer, Sudarshan Srinivasan, Gregg William Baeckler, Duncan Moss, Sasikanth Avancha, Dipankar Das
  • Publication number: 20220078107
    Abstract: A computing system is provided, including a processor configured to receive a directed acyclic graph (DAG) template specifying a data pipeline of a plurality of processing stages. For each processing stage, the processor may be further configured to select a respective processing device of a plurality of communicatively linked processing devices. The processor may be further configured to determine a routing sequence between the plurality of processing devices according to the DAG template. The processor may be further configured to transmit a plurality of input packets encoding the plurality of processing stages to the respective processing devices selected for the processing stages as specified by the routing sequence. In response to transmitting the plurality of input packets, the processor may be further configured to receive, from a processing device of the plurality of processing devices, one or more output packets encoding a processing result of the data pipeline.
    Type: Application
    Filed: September 8, 2020
    Publication date: March 10, 2022
    Inventors: Suchit Subhaschandra, Jonathan Beare, Duncan Moss
  • Publication number: 20190042939
    Abstract: The present disclosure relates generally to techniques for improving the implementation of certain operations on an integrated circuit. In particular, deep learning techniques, which may use a deep neural network (DNN) topology, may be implemented more efficiently using low-precision weights and activation values by efficiently performing down conversion of data to a lower precision and by preventing data overflow during suitable computations. Further, by more efficiently mapping multipliers to programmable logic on the integrated circuit device, the resources used by the DNN topology to perform, for example, inference tasks may be reduced, resulting in improved integrated circuit operating speeds.
    Type: Application
    Filed: May 31, 2018
    Publication date: February 7, 2019
    Inventors: Martin Langhammer, Sudarshan Srinivasan, Gregg William Baeckler, Duncan Moss, Sasikanth Avancha, Dipankar Das