Patents by Inventor Duncan Pilgrim

Duncan Pilgrim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11164801
    Abstract: An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped or the like, and singulated. The singulated dies, which may be of different sizes and functionality, are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Sets of dies of different functionality may be tested as a system or subsystem. Once test probing is complete, the dies (or sets of dies) and tile are singulated into die/tile assemblies.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: November 2, 2021
    Assignee: pSemi Corporation
    Inventors: Mark Moffat, Andrew Christie, Duncan Pilgrim, Ronald Eugene Reedy
  • Publication number: 20200365470
    Abstract: An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped or the like, and singulated. The singulated dies, which may be of different sizes and functionality, are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Sets of dies of different functionality may be tested as a system or subsystem. Once test probing is complete, the dies (or sets of dies) and tile are singulated into die/tile assemblies.
    Type: Application
    Filed: May 27, 2020
    Publication date: November 19, 2020
    Inventors: Mark Moffat, Andrew Christie, Duncan Pilgrim, Ronald Eugene Reedy
  • Patent number: 10699970
    Abstract: An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped or the like, and singulated. The singulated dies, which may be of different sizes and functionality, are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Sets of dies of different functionality may be tested as a system or subsystem. Once test probing is complete, the dies (or sets of dies) and tile are singulated into die/tile assemblies.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: June 30, 2020
    Assignee: pSemi Corporation
    Inventors: Mark Moffat, Andrew Christie, Duncan Pilgrim, Ronald Eugene Reedy
  • Publication number: 20190096772
    Abstract: An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped or the like, and singulated. The singulated dies, which may be of different sizes and functionality, are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Sets of dies of different functionality may be tested as a system or subsystem. Once test probing is complete, the dies (or sets of dies) and tile are singulated into die/tile assemblies.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 28, 2019
    Inventors: Mark Moffat, Andrew Christie, Duncan Pilgrim, Ronald Eugene Reedy
  • Patent number: 10109537
    Abstract: An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped, and singulated. The singulated dies are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Once test probing is complete, the dies and tile are singulated into die/tile assemblies.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: October 23, 2018
    Assignee: pSemi Corporation
    Inventors: Mark Moffat, Andrew Christie, Duncan Pilgrim
  • Publication number: 20180211890
    Abstract: An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped, and singulated. The singulated dies are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Once test probing is complete, the dies and tile are singulated into die/tile assemblies.
    Type: Application
    Filed: October 31, 2017
    Publication date: July 26, 2018
    Inventors: Mark Moffat, Andrew Christie, Duncan Pilgrim
  • Patent number: 9837325
    Abstract: An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped, and singulated. The singulated dies are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Once test probing is complete, the dies and tile are singulated into die/tile assemblies.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: December 5, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Mark Moffat, Andrew Christie, Duncan Pilgrim
  • Publication number: 20160372387
    Abstract: An extension of conventional IC fabrication processes to include some of the concepts of flip-chip assemblies while producing a final “non-flip chip” circuit structure suitable for conventional packaging or for direct usage by customers. Multiple IC dies are fabricated on a semiconductor wafer in a conventional fashion, solder bumped, and singulated. The singulated dies are then flip-chip assembled onto a single tile substrate of thin-film material which has been patterned with vias, peripheral connection pads, and one or more ground planes. Once dies are flip-chip mounted to the thin-film tile, all of the dies on the entire tile may be probed using automated testing equipment. Once test probing is complete, the dies and tile are singulated into die/tile assemblies.
    Type: Application
    Filed: June 16, 2015
    Publication date: December 22, 2016
    Inventors: Mark Moffat, Andrew Christie, Duncan Pilgrim