Abstract: Disclosed herein are a product containing an extract from Zanthoxylum avicennae (Lam.) DC. and a process for preparing the same. Also disclosed herein are a pharmaceutical composition including the aforesaid product containing the extract from Zanthoxylum avicennae (Lam.) DC., a method of treating a cancer in a subject via the aforementioned pharmaceutical composition, and a method of inhibiting tumor/cancer cells by virtue of the aforesaid product containing the extract from Zanthoxylum avicennae (Lam.) DC.

Abstract: An apparatus for engaging and moving a ram block. In some embodiments, the apparatus, or ram block changer, includes a support bracket coupled to a blowout preventer and an articulated arm releasably coupled to the ram block. The ram block changer may further include a pivot coupling assembly having a first axis of rotation. The pivot coupling assembly extends through the support bracket and the articulated arm, wherein the articulated arm is rotatable about the first axis of rotation relative to the support bracket. The articulated aim may include a first member receiving the pivot coupling assembly therethrough, a second member coupled to the ram block, and a second pivot coupling assembly having a second axis of rotation spaced apart from the first axis of rotation and extending through the first and second members. The second member is rotatable about the second axis of rotation relative to the first member.

Abstract: Multistage signal amplification, including level translation, improves signal integrity, e.g., slew rate, complementary signal delay and duty cycle performance, by mirroring complementary output current in an output stage based on a signal developed in an input stage pull-up network. A multistage amplifier may comprise a first stage comprising a differential input circuit coupled, respectively, between first and second inputs and first and second nodes, wherein the first node is coupled to a first pull-up circuit controlled by the first node and the second node is coupled to a second pull-up circuit controlled by the second node; and a second stage comprising a complementary output circuit coupled, respectively, between first and second nodes and first and second outputs, wherein a current mirror sinks essentially the same current at the first output as is sourced at the second output and vice versa. The pull-up network may further comprise a cross-coupled pull-up circuit.

Abstract: A central body, preferably circular or rotund, has a plurality of elongated arms radiating out from it. Each arm includes a rigid blade end that defines a profile that operationally fits over a fingernail at an angle of incidence for masking an area of the fingernail during painting, or for scoring semi-hardened paint and scraping off excess paint. Angle of incidence is preferably acute, obtuse or right. Each blade end preferably operationally fits over a uniquely corresponding relatively small range of fingernail sizes. The end blades are disposed in order in a direction around the body, the order being progressively larger range sizes. A mark on each end blade is used for aligning the end blade with a longitudinal axis of a fingernail.

Abstract: Methods and apparatus for applying a single virtual private network (VPN) address to tunnels or connections associated with different access interfaces are disclosed. In one embodiment, a method includes establishing a first tunnel between a node and a VPN server. The first tunnel has a first address. The method also includes assigning a VPN address to the first tunnel, as well as establishing a second tunnel between the node and the VPN server. The second tunnel has a second address. The VPN address is assigned to the second tunnel, and VPN address is accessed by both the first address and the second address.

Abstract: A discharge lamp lighting control device (100) having a DC power converter, a power factor improving power converter (1), a polarity reversing circuit (2), a starter circuit (3), and a controller (4). The power factor improving power converter 1 includes a switching device S, a power factor improver, and a power converter. The power factor improver operates to smooth a rectified voltage by storing energy in a first inductive device L1 and by discharging energy from a second inductive device L2, in which the first and second inductive devices are magnetically coupled together. The storing and discharging is performed by turning ON and OFF the switching device S. A predetermined DC voltage is converted by energy stored and discharged by a third inductive device L3 in response to the turning ON and OFF of the switching device S.

Abstract: A discharge lamp lighting control device (100) having a DC power converter, a power factor improving power converter (1), a polarity reversing circuit (2), a starter circuit (3), and a controller (4). The power factor improving power converter 1 includes a switching device S, a power factor improver, and a power converter. The power factor improver operates to smooth a rectified voltage by storing energy in a first inductive device L1 and by discharging energy from a second inductive device L2, in which the first and second inductive devices are magnetically coupled together. The storing and discharging is performed by turning ON and OFF the switching device S. A predetermined DC voltage is converted by energy stored and discharged by a third inductive device L3 in response to the turning ON and OFF of the switching device S.

Abstract: A memory array contains memory cells designed to be erased using Fowler-Nordheim (“FN”) tunneling through the channel area, and programmed using either channel hot electron injection (“CHE”) or channel-initiated secondary electron injection (“CISEI”). To reduce disturbance of the floating gate potential of unselected memory cells during programming operations and read operations, the unselected word lines are brought to a negative potential rather than ground potential. To reduce disturbance of the floating gate potential of unselected memory cells during FN erase operations, the unselected word lines are brought to a positive potential rather than ground potential.

Abstract: A memory array contains memory cells designed to be erased using Fowler-Nordheim (“FN”) tunneling through the channel area, and programmed using either channel hot electron injection (“CHE”) or channel-initiated secondary electron injection (“CISEI”). To reduce disturbance of the floating gate potential of unselected memory cells during programming operations and read operations, the unselected word lines are brought to a negative potential rather than ground potential. To reduce disturbance of the floating gate potential of unselected memory cells during FN erase operations, the unselected word lines are brought to a positive potential rather than ground potential.

Abstract: A convergence signal includes a series of voltage pulses used to perform a convergence procedure in one or more flash EEPROM memory cells (transistors). In one instance subsequent voltage pulses in the convergence signal each have a higher voltage than the preceding pulse. In another instance, subsequent voltage pulses in the convergence signal each have a longer duration than the preceding pulse. An integrated circuit includes an array of memory cells and an erase control unit which controls the application of the convergence signal to one or more memory cells. The integrated circuit may be either serial or parallel flash EEPROM in which bulk, sector, or page mode erasing is used.

Abstract: A convergence signal includes a series of voltage pulses used to perform a convergence procedure in one or more flash EEPROM memory cells (transistors). In one instance subsequent voltage pulses in the convergence signal each have a higher voltage than the preceding pulse. In another instance, subsequent voltage pulses in the convergence signal each have a longer duration than the preceding pulse. An integrated circuit includes an array of memory cells and an erase control unit which controls the application of the convergence signal to one or more memory cells. The integrated circuit may be either serial or parallel flash EEPROM in which bulk, sector, or page mode erasing is used.

Abstract: A memory array contains memory cells designed to be erased using Fowler-Nordheim (“FN”) tunneling through the channel area, and programmed using either channel hot electron injection (“CHE”) or channel-initiated secondary electron injection (“CISEI”). To reduce disturbance of the floating gate potential of unselected memory cells during programming operations and read operations, the unselected word lines are brought to a negative potential rather than ground potential. To reduce disturbance of the floating gate potential of unselected memory cells during FN erase operations, the unselected word lines are brought to a positive potential rather than ground potential.

Abstract: A memory array contains memory cells designed to be erased using Fowler-Nordheim (“FN”) tunneling through the channel area, and programmed using either channel hot electron injection (“CHE”) or channel-initiated secondary electron injection (“CISEI”). To reduce disturbance of the floating gate potential of unselected memory cells during programming operations and read operations, the unselected word lines are brought to a negative potential rather than ground potential. To reduce disturbance of the floating gate potential of unselected memory cells during FN erase operations, the unselected word lines are brought to a positive potential rather than ground potential.

Abstract: A technique for detecting failed batteries while the battery is attached to one or more electronic devices and is receiving a float charge is disclosed. The float voltage minimizes the normal voltage differences between battery cells. The technique employs a ratio comparative analysis of cell voltages of a battery provided across the terminals of the battery. Application of the ratio comparative analysis in assessing the condition of a battery assumes an equal voltage drop across each battery cell such that the cells are modeled as a series of resisters with respect to the float voltage. Such equal voltage drop enables a comparative ratio analysis of the voltage across each of the two portions of the battery's cell stack to the voltage across the entire battery. The comparative ratio analysis determines a voltage threshold that identifies whether a battery has a shorted or open cell.